AD7492BRU-5(Rev0) データシートの表示（PDF） - Analog Devices
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AD7492BRU-5 Datasheet PDF : 16 Pages
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AD7492
TIMING SPECIFICATIONS1 (VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
AD7492
AD7492-52
Unit
Description
tCONVERT
tWAKEUP
880
203
500
t1
10
t2
10
40
t3
0
t44
0
t5
20
t64
15
t75
8
t8
0
t9
120
t10
100
680
ns max
203
µs max
Partial Sleep Wake-Up Time
500
µs max
Full Sleep Wake-Up Time
10
ns min
CONVST Pulsewidth
10
ns max
CONVST to BUSY Delay, VDD = 5 V
N/A
ns max
CONVST to BUSY Delay, VDD = 3 V
0
ns max
BUSY to CS Setup Time
0
ns max
CS to RD Setup Time
20
ns min
RD Pulsewidth
15
ns min
Data Access Time after Falling Edge of RD
8
ns max
Bus Relinquish Time after Rising Edge of RD
0
ns max
CS to RD Hold Time
120
ns min
Acquisition Time
100
ns min
Quiet Time
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See
Figure 1.
2The AD7492-5 is specified with VDD = 4.75 V to 5.25 V.
3This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 µs, but we cannot guarantee that the part
will sample within 0.5 LSB of the true analog input value. Therefore we recommend that the user does not start conversion until after the specified time.
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
5t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200A
IOL
TO OUTPUT
PIN
CL
50pF
200A
IOH
1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
–4–
REV. 0
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