AD7492(Rev0) データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD7492
(Rev.:Rev0)

1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC

Analog Devices 

AD7492

1

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

512 1023 1534 2045 2556 3067 3578 4089

CODE

TPC 7. Typical INL for 2.75 V @ 25°C

1

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

512 1023 1534 2045 2556 3067 3578 4089

CODE

TPC 8. Typical DNL for 2.75 V @ 25°C

CIRCUIT DESCRIPTION

CONVERTER OPERATION

The AD7492 is a 12-bit successive approximation analog-to-

digital converter based around a capacitive DAC. The AD7492

can convert analog input signals in the range 0 V to VREF. Figure 2

shows a very simplified schematic of the ADC. The Control

Logic, SAR, and the Capacitive DAC are used to add and sub-

tract fixed amounts of charge from the sampling capacitor to

bring the comparator back into a balanced condition.

CAPACITIVE

DAC

COMPARATOR

VIN

VREF

SWITCHES

SAR

Figure 3 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in Position A. The comparator is held in a

balanced condition and the sampling capacitor acquires the

signal on VIN.

CAPACITIVE

DAC

VIN

A

SW1 B

2k⍀

SW2

CONTROL LOGIC

AGND

COMPARATOR

Figure 3. ADC Acquisition Phase

Figure 4 shows the ADC during conversion. When conversion

starts, SW2 will open and SW1 will move to Position B, causing

the comparator to become unbalanced. The ADC then runs

through its successive approximation routine and brings the com-

parator back into a balanced condition. When the comparator is

rebalanced, the conversion result is available in the SAR register.

CAPACITIVE

DAC

VIN

AGND

A

SW1 B

2k⍀

SW2

CONTROL LOGIC

COMPARATOR

Figure 4. ADC Conversion Phase

TYPICAL CONNECTION DIAGRAM

Figure 5 shows a typical connection diagram for the AD7492.

Conversion is initiated by a falling edge on CONVST. Once

CONVST goes low the BUSY signal goes high, and at the end

of conversion the falling edge of BUSY is used to activate an

Interrupt Service Routine. The CS and RD lines are then activated

in parallel to read the 12 data bits. The internal bandgap reference

voltage is 2.5 V, providing an analog input range of 0 V to 2.5 V,

making the AD7492 a unipolar A/D. A capacitor with a mini-

mum capacitance of 100 nF is needed at the output of the REF

OUT pin as it stabilizes the internal reference value. It is recom-

mended to perform a dummy conversion after power-up as the

first conversion result could be incorrect. This also ensures that

the part is in the correct mode of operation. The CONVST pin

should not be floating when power is applied as a rising edge on

CONVST might not wake up the part.

In Figure 5 the VDRIVE pin is tied to DVDD, which results in logic

output voltage values being either 0 V or DVDD. The voltage

applied to VDRIVE controls the voltage value of the output logic

signals and the input logic signals. For example, if DVDD is

supplied by a 5 V supply and VDRIVE by a 3 V supply, the logic

output voltage levels would be either 0 V or 3 V. This feature

allows the AD7492 to interface to 3 V parts while still enabling

the A/D to process signals at 5 V supply.

CONTROL

INPUTS

CONTROL LOGIC

OUTPUT DATA

12-BIT PARALLEL

Figure 2. Simplified Block Diagram of AD7492

REV. 0

–9–

Share Link: