EVAL-AD7492CB データシートの表示（PDF） - Analog Devices

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EVAL-AD7492CB

1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC

Analog Devices 

AD7492

CIRCUIT DESCRIPTION

CONVERTER OPERATION

The AD7492 is a 12-bit successive approximation analog-to-

digital converter based around a capacitive DAC. The AD7492

can convert analog input signals in the range 0 V to VREF. Figure

12 shows a very simplified schematic of the ADC. The control

logic, SAR register, and capacitive DAC are used to add and

subtract fixed amounts of charge from the sampling capacitor to

bring the comparator back into a balanced condition.

COMPARATOR

CAPACITIVE

DAC

VREF

VIN

SWITCHES

SAR

CONTROL

INPUTS

CONTROL LOGIC

OUTPUT DATA

12-BIT PARALLEL

Figure 12. Simplified Block Diagram of AD7492

Figure 13 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in Position A. The comparator is held in a

balanced condition and the sampling capacitor acquires the

signal on VIN.

CAPACITIVE

DAC

VIN

AGND

A

SW1 B

2kΩ

SW2

CONTROL LOGIC

COMPARATOR

Figure 13. ADC Acquisition Phase

Figure 14 shows the ADC during conversion. When conversion

starts, SW2 opens and SW1 moves to Position B, causing the

comparator to become unbalanced. The ADC then runs

through its successive approximation routine and brings the

comparator back into a balanced condition. When the

comparator is rebalanced, the conversion result is available in

the SAR register.

A

VIN

SW1 B

AGND

2kΩ

SW2

CAPACITIVE

DAC

CONTROL LOGIC

COMPARATOR

TYPICAL CONNECTION DIAGRAM

Figure 15 shows a typical connection diagram for the AD7492.

Conversion is initiated by a falling edge on CONVST. Once

CONVST goes low the BUSY signal goes high, and at the end of

the conversion, the falling edge of BUSY is used to activate an

interrupt service routine. The CS and RD lines are then activated

in parallel to read the 12 data bits. The internal band gap

reference voltage is 2.5 V, providing an analog input range of 0 V

to 2.5 V, making the AD7492 a unipolar A/D. A capacitor with a

minimum capacitance of 100 nF is needed at the output of the

REF OUT pin as it stabilizes the internal reference value. It is

recommended to perform a dummy conversion after power-up as

the first conversion result could be incorrect. This also ensures

that the part is in the correct mode of operation. The CONVST

pin should not be floating when power is applied, as a rising edge

on CONVST might not wake up the part.

In Figure 15 the VDRIVE pin is tied to DVDD, which results in

logic output voltage values being either 0 V or DVDD. The

voltage applied to VDRIVE controls the voltage value of the output

logic signals and the input logic signals. For example, if DVDD is

supplied by a 5 V supply and VDRIVE by a 3 V supply, the logic

output voltage levels would be either 0 V or 3 V. This feature

allows the AD7492 to interface to 3 V parts while still enabling

the A/D to process signals at 5 V supply.

+

10µF

ANALOG

0.1µF

+

47µF

SUPPLY

2.7V TO 5.25V

µC/µP

1nF

2.5V

100nF

PARALLELED

INTERFACE

VDRIVE AVDD

DVDD

AD7492

REF OUT

VIN

DB0 TO

DB9 (DB11)

CS

CONVST

RD

BUSY

PS/FS

0V TO 2.5V

Figure 15. Typical Connection Diagram

ADC TRANSFER FUNCTION

The output coding of the AD7492 is straight binary. The

designed code transitions occur at successive integer LSB values

(that is, 1 LSB, 2 LSB, etc.). The LSB size equals 2.5/4096 for the

AD7492. The ideal transfer characteristic for the AD7492 is

shown in Figure 16.

Figure 14. ADC Conversion Phase

Rev. A | Page 13 of 24

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