EVAL-AD7492CB データシートの表示（PDF） - Analog Devices

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EVAL-AD7492CB

1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC

Analog Devices 

AD7492

80C186 to AD7492 Interface

Figure 33 shows the AD7492 interfaced to the 80C186

microprocessor. The 80C186 DMA controller provides two

independent high speed DMA channels where data transfer can

occur between memory and I/O spaces. (The AD7492 occupies

one of these I/O spaces.) Each data transfer consumes two bus

cycles, one cycle to fetch data and the other to store data.

After the AD7492 has finished the conversion, the BUSY line

generates a DMA request to Channel 1 (DRQ1). Because of the

interrupt, the processor performs a DMA read operation that

resets the interrupt latch. Sufficient priority must be assigned to

the DMA channel to ensure that the DMA request is serviced

before the completion of the next conversion. This

configuration can be used with 6 MHz and 8 MHz 80C186

processors.

AD0 TO AD15

A16 TO A19

ALE

80C1861

ADDRESS/DATA BUS

ADDRESS

LATCH

ADDRESS

BUS

ADDRESS

DECODER

OPTIONAL

CONVST

AD7492

CS

DRQ1

RD

QR

S

DATA BUS

BUSY

RD

DB0 TO DB9

(DB11)

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 33. 80C186 to AD7492 Interface

Rev. A | Page 20 of 24

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