AD7451BRT データシートの表示（PDF） - Analog Devices
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AD7451BRT Datasheet PDF : 15 Pages
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PRELIMINARY TECHNICAL DATA
AD7451/AD7441
TIMING SPECIFICATIONS 1,2
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; FIN = 300kHz;
TA = TMIN to TMAX, unless otherwise noted.)
Limit at
Parameter TMIN, TMAX Units
Description
fSCLK 4
tCONVERT
tQUIET
t1
t2
t
5
3
t
5
4
t5
t6
t7
t
6
8
tPOWER-UP7
10
18
16 x tSCLK
888
25
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
kHz min
MHz max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
tSCLK = 1/fSCLK
Minimum Quiet Time between the End of a Serial Read and the
Next Falling Edge of CS
Minimum CS Pulsewidth
CS falling Edge to SCLK Falling Edge Setup Time
Delay from CS Falling Edge Until SDATA 3-State Disabled
Data Access Time After SCLK Falling Edge
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Edge to Data Valid Hold Time
SCLK Falling Edge to SDATA 3-State Enabled
SCLK Falling Edge to SDATA 3-State Enabled
Power-Up Time from Full Power-Down
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts.
2See Figure 1, Figure 2 and the ‘Serial Interface’ section.
3Common Mode Voltage.
4Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and time for
an output to cross 0.4 V or 2.0 V for VDD = 3 V.
6t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured num-
ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
7 See ‘Power-up Time’ Section.
Specifications subject to change without notice.
t1
+5
SCLK
SDATA
+5
t CONVERT
t2
t5
1
2
3
4
5
t7
t3
t4
B
13
14
t6
15
16
t8
t QUIET
0
0
0
0
DB11 DB10
DB2
DB1
DB0
4 LEADING ZERO’S
Figure 1. AD7451 Serial Interface Timing Diagram
3-STATE
t1
SCLK
SDATA
t CONVERT
t2
t5
1
2
3
4
5
t7
t3
t4
B
13
14
t6
15
16
t8
t QUIET
0
0
0
0
DB9
DB8
DB0
0
0
4 LEADING ZERO’S
3-STATE
2 TRAILING ZEROS
Figure 2. AD7441 Serial Interface Timing Diagram
–6–
REV. PrC
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