EVAL-AD7622CB データシートの表示（PDF） - Analog Devices
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EVAL-AD7622CB Datasheet PDF : 28 Pages
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AD7622
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND 1
AVDD 2
DGND 3
BYTESWAP 4
OB/2C 5
WARP 6
NORMAL 7
SER/PAR 8
D0 9
D1 10
D2/DIVSCLK[0] 11
D3/DIVSCLK[1] 12
NC = NO CONNECT
AD7622
TOP VIEW
(Not to Scale)
36 AGND
35 CNVST
34 PD
33 RESET
32 CS
31 RD
30 DGND
29 BUSY
28 D15
27 D14
26 D13
25 D12
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1
AVDD 2
DGND 3
BYTESWAP 4
OB/2C 5
WARP 6
NORMAL 7
SER/PAR 8
D0 9
D1 10
D2/DIVSCLK[0] 11
D3/DIVSCLK[1] 12
PIN 1
IDENTIFIER
AD7622
TOP VIEW
(Not to Scale)
36 AGND
35 CNVST
34 PD
33 RESET
32 CS
31 RD
30 DGND
29 BUSY
28 D15
27 D14
26 D13
25 D12
NC = NO CONNECT
13 14 15 16 17 18 19 20 21 22 23 24
Figure 5. 48-Lead LFCSP Pin Configuration
Figure 6. 48-Lead LQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin
No. Mnemonic
Type1 Description
1, 36, AGND
41, 42
P
Analog Power Ground.
2, 44 AVDD
P
Input Analog Power Pins. Nominally 2.5 V.
3
DGND
P
Digital Power Ground.
4
BYTESWAP
DI
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
OB/2C
DI
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary;
when low, the MSB is inverted resulting in a twos complement output from its internal shift register.
6
WARP
DI
Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp
mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects
warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and
a minimum conversion rate must be applied to guarantee full specified accuracy.
7
NORMAL
DI
Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode
where full accuracy is maintained independent of the minimum conversion rate.
8
SER/PAR
DI/O Serial/Parallel Selection Input.
When SER/PAR = high, the serial interface is selected and some bits of the data bus are used as a
serial port; the remaining data bits are high impedance outputs.
When SER/PAR = low, the parallel port is selected.
9, 10 D[0:1]
DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of
the interface mode.
11, 12 D[2:3]
DI/O When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
or DIVSCLK[0:1]
When SER/PAR = high, serial clock division selection. When using serial master read after convert mode
(EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated
serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
Rev. A | Page 8 of 28
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