EVAL-AD7655CB データシートの表示（PDF） - Analog Devices
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EVAL-AD7655CB Datasheet PDF : 28 Pages
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AD7655
Parameter
SLAVE SERIAL INTERFACE MODES (See Figure 31 and Figure 32)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
Symbol Min Typ
t38
5
t39
3
t40
5
t41
5
t42
25
t43
10
t44
10
Max
18
1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise CL is 60 pF maximum.
2 In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Unit
ns
ns
ns
ns
ns
ns
ns
Table 4. Serial Clock Timings in Master Read After Convert
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
SYNC to SCLK First Edge Delay Minimum
t25
3
17
17
17
ns
Internal SCLK Period Minimum
t26
25
50
100
200
ns
Internal SCLK Period Typical
t26
40
70
140
280
ns
Internal SCLK High Minimum
t27
12
22
50
100
ns
Internal SCLK Low Minimum
t28
7
21
49
99
ns
SDOUT Valid Setup Time Minimum
t29
4
18
18
18
ns
SDOUT Valid Hold Time Minimum
t30
2
4
30
80
ns
SCLK Last Edge to SYNC Delay Minimum
t31
1
3
30
80
ns
Busy High Width Maximum (Normal)
t35
3.25
4.25
6.25
10.75
μs
Busy High Width Maximum (Impulse)
t35
3.5
4.5
6.5
11
μs
Rev. B | Page 6 of 28
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