AD76881 データシートの表示（PDF） - Analog Devices
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AD76881 Datasheet PDF : 28 Pages
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AD7986
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode)
Acquisition Time
Time Between Conversions (Turbo Mode/Normal Mode)
CNV Pulse Width (CS Mode)
Data Read During Conversion (Turbo Mode/Normal Mode)
Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Symbol
tCONV
tACQ
tCYC
tCNVH
tDATA
tQUIET
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min
Typ
100
500/660
10
20
9
11
3.5
3.5
2
4
0
0
5
5
2
3
Max
Unit
400/500 ns
ns
ns
ns
200/300 ns
ns
ns
ns
ns
ns
ns
6
ns
10
ns
8
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
1 See Figure 2 and Figure 3 for load conditions.
500µA IOL
TO SDO
CL
20pF
1.4V
500µA IOH
Figure 2. Load Circuit for Digital Interface Timing
90% VIO
tDELAY
VIH1
VIL1
10% VIO
tDELAY
VIH1
VIL1
1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. B | Page 5 of 28
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