AD7680 データシートの表示（PDF） - Analog Devices

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AD7680

3 mW, 100 kSPS, 16-Bit ADC in 6-Lead SOT-23

Analog Devices 

ADC TRANSFER FUNCTION

The output coding of the AD7680 is straight binary. The

designed code transitions occur at successive integer LSB

values, i.e., 1 LSB, 2 LSBs. The LSB size is VDD/65536. The ideal

transfer characteristic for the AD7680 is shown in Figure 14.

111...111

111...110

111...000

011...111

1 LSB = VDD/65536

000...010

000...001

000...000

0V

1 LSB

ANALOG INPUT

+VDD–1 LSB

Figure 14. AD7680 Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 15 shows a typical connection diagram for the AD7680.

VREF is taken internally from VDD and as such should be well

decoupled. This provides an analog input range of 0 V to VDD.

The conversion result is output in a 24-bit word, or alternatively,

all 16 bits of the conversion result may be accessed using a

minimum of 20 SCLKs. This 20-/24-bit data stream consists of

a four leading zeros, followed by the 16 bits of conversion data,

followed by four trailing zeros in the case of the 24 SCLK

transfer. For applications where power consumption is of

concern, the power-down mode should be used between

conversions or bursts of several conversions to improve power

performance (see the Modes of Operation section).

AD7680

In fact, because the supply current required by the AD7680 is so

low, a precision reference can be used as the supply source to

the AD7680. For example, a REF19x voltage reference (REF195

for 5 V or REF193 for 3 V) or an AD780 can be used to supply

the required voltage to the ADC (see Figure 15). This

configuration is especially useful if the power supply available is

quite noisy, or if the system supply voltages are at some value

other than the required operating voltage of the AD7680, e.g.,

15 V. The REF19x or AD780 outputs a steady voltage to the

AD7680. Recommended decoupling capacitors are a 100 nF low

ESR ceramic (Farnell 335-1816) and a 10 μF low ESR tantalum

(Farnell 197-130).

10F

TANT

3V

0.1F

REF193

10F

0.1F

5V

SUPPLY

0V TO VDD

INPUT

VDD

VIN

AD7680

GND

SCLK

SDATA

CS

C/P

SERIAL

INTERFACE

Figure 15. Typical Connection Diagram

Digital Inputs

The digital inputs applied to the AD7680 are not limited by the

maximum ratings that limit the analog inputs. Instead, the

digital inputs applied can go to 7 V and are not restricted by the

VDD + 0.3 V limit as on the analog inputs. For example, if the

AD7680 were operated with a VDD of 3 V, 5 V logic levels could

be used on the digital inputs. However, it is important to note

that the data output on SDATA still has 3 V logic levels when

VDD = 3 V.

Another advantage of SCLK and CS not being restricted by the

VDD + 0.3 V limit is that power supply sequencing issues are

avoided. If one of these digital inputs is applied before VDD, then

there is no risk of latch-up as there would be on the analog

inputs if a signal greater than 0.3 V were applied prior to VDD.

Rev. A | Page 13 of 24

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