AD7680 データシートの表示（PDF） - Analog Devices

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AD7680

3 mW, 100 kSPS, 16-Bit ADC in 6-Lead SOT-23

Analog Devices 

AD7680

It is also possible to take valid data on each SCLK rising edge

rather than falling edge, since the SCLK cycle time is long

enough to ensure the data is ready on the rising edge of SCLK.

However, the first leading zero is still driven by the CS falling

edge, and so it can be taken on only the first SCLK falling edge.

It may be ignored and the first rising edge of SCLK after the CS

falling edge would have the second leading zero provided and

the 23rd rising SCLK edge would have the final trailing zero

provided. This method may not work with most

microcontrollers/DSPs but could possibly be used with FPGAs

and ASICs.

AD7680 TO ADSP-218x

The ADSP-218x family of DSPs can be interfaced directly to the

AD7680 without any glue logic required. The SPORT control

register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 0111, 8-Bit Data-Words

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 0, Frame First Word

IRFS = 0

ITFS = 1

To implement the power-down mode, SLEN should be set to

0111 to issue an 8-bit SCLK burst. The connection diagram is

shown in Figure 22. The ADSP-218x has the TFS and RFS of the

SPORT tied together, with TFS set as an output and RFS set as

an input. The DSP operates in alternate framing mode and the

SPORT control register is set up as described. Transmit and

receive autobuffering is used in order to get a 24 SCLK transfer.

Each buffer contains three 8-bit words. The frame synchroniza-

tion signal generated on the TFS is tied to CS, and as with all

signal processing applications, equidistant sampling is necessary.

In this example, the timer interrupt is used to control the

sampling rate of the ADC.

AD7680*

SCLK

SDATA

CS

ADSP-218x*

SCLK

DR

RFS

TFS

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 22. Interfacing to the ADSP-218x

The timer register is loaded with a value that provides an

interrupt at the required sample interval. When an interrupt is

received, the values in the transmit autobuffer start to be

transmitted and TFS is generated. The TFS is used to control

the RFS and therefore the reading of data. The data is stored in

the receive autobuffer for processing or to be shifted later. The

frequency of the serial clock is set in the SCLKDIV register.

When the instruction to transmit with TFS is given, i.e.,

TX0 = AX0, the state of the SCLK is checked. The DSP waits

until the SCLK has gone high, low, and high again before

transmission starts. If the timer and SCLK values are chosen

such that the instruction to transmit occurs on or near the

rising edge of SCLK, the data may be transmitted or it may wait

until the next clock edge.

Rev. A | Page 18 of 24

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