AD7680 データシートの表示（PDF） - Analog Devices
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AD7680 Datasheet PDF : 24 Pages
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AD7680
TIMING SPECIFICATIONS1
Table 4. VDD = 2.5 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted.
Limit at TMIN, TMAX
Parameter 3 V
5V
Unit
Description
fSCLK 2
250
250
kHz min
2.5
2.5
MHz max
tCONVERT
20 × tSCLK 20 × tSCLK min
tQUIET
100
100
ns min Minimum quiet time required between bus relinquish and start of next conversion
t1
10
10
ns min
Minimum CS pulse width
t2
10
10
ns min
CS to SCLK setup time
t3 3
48
35
ns max Delay from CS until SDATA three-state disabled
t43
120
80
ns max Data access time after SCLK falling edge
t5
0.4 tSCLK 0.4 tSCLK ns min
SCLK low pulse width
t6
0.4 tSCLK 0.4 tSCLK ns min
SCLK high pulse width
t7
10
10
ns min SCLK to data valid hold time
t8 4
45
35
ns max SCLK falling edge to SDATA high impedance
tPOWER-UP 5
1
1
μs typ
Power up time from full power-down
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5 See Power vs. Throughput Rate section.
200μA
IOL
TO OUTPUT
PIN CL
50pF
200μA
IOH
1.6V
Figure 2. Load Circuit for Digital Output Timing Specification
Rev. A | Page 6 of 24
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