AD7740YRT データシートの表示（PDF） - Analog Devices

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AD7740YRT

3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter

Analog Devices 

AD7740

GENERAL DESCRIPTION

The AD7740 is a CMOS synchronous Voltage-to-Frequency

Converter (VFC) which uses a charge-balance conversion

technique. The input voltage signal is applied to a proprietary

front-end based around an analog modulator which converts the

input voltage into an output pulse train.

The part also contains an on-chip 2.5 V bandgap reference and

operates from a single 3.3 V or 5 V supply. A block diagram of

the AD7740 is shown in Figure 3.

INTEGRATOR

COMPARATOR

VIN

SWITCHED

CAPS

FOUT

BUF

SWITCHED

CAPS

GND

AD7740

Figure 3. Block Diagram

Input Amplifier Buffering and Voltage Range

The analog input VIN can be buffered by setting BUF = 1. This

presents a high impedance, typically 100 MΩ, which allows

significant external source impedances to be tolerated. The VIN

voltage range is now 0.1 V to VDD – 0.2 V. By setting BUF = 0

the AD7740 input circuit accepts an analog input below GND

and the analog input VIN has a voltage range from –0.15 V to

VDD + 0.15 V. In this case the input impedance is typically

650 kΩ.

The transfer function for the AD7740 is represented by:

FOUT = 0.1 fCLKIN + 0.8 (VIN/VREF) fCLKIN

It is shown in Figure 4 for unbuffered mode.

FOUT MAX

0.90 fCLKIN

OUTPUT

FREQUENCY

FOUT

AD7740

VFC Modulator

The analog input signal to the AD7740 is continuously sampled

by a switched capacitor modulator whose sampling rate is set

by a master clock. The input signal may be buffered on-chip

(BUF = 1) before being applied to the sampling capacitor of the

modulator. This isolates the sampling capacitor charging currents

from the analog input pin.

This system is a negative feedback loop that acts to keep the net

charge on the integrator capacitor at zero, by balancing charge

injected by the input voltage with charge injected by VREF. The

output of the comparator provides the digital input for the 1-bit

DAC, so that the system functions as a negative feedback loop

that acts to minimize the difference signal. See Figure 5.

INPUT

INTEGRATOR

CLK

COMPARATOR

1-BIT

BITSTREAM

+VREF

AD7740

–VREF

Figure 5. Modulator Loop

The digital data that represents the analog input voltage is con-

tained in the duty cycle of the pulse train appearing at the output

of the comparator. The output is a pulse train whose frequency

depends on the analog input signal. A full-scale input gives an

output frequency of 0.9 fCLKIN and zero-scale input gives an

output frequency of 0.1 fCLKIN. The output allows simple inter-

facing to either standard logic families or opto-couplers. The

pulsewidth of FOUT is fixed and is determined by the high period

of CLKIN. The pulse is synchronized to the rising edge of the

clock signal. The delay time between the edge of CLKIN and the

edge of FOUT is typically 35 ns. Figure 6 shows the waveform

of this frequency output. (See TPC 8.)

fCLKIN

0.10 fCLKIN

FOUT MIN

–0.15V 0

VREF VREF + 0.15V

Figure 4. Transfer Function

INPUT

VOLTAGE

VIN

Sample Calculation:

VREF = 2.5 V, BUF = 0

FOUT (min) = 0.1 fCLKIN + 0.8(–0.15/2.5) fCLKIN

= 0.052 fCLKIN

FOUT (max) = 0.1 fCLKIN + 0.8(2.65/2.5) fCLKIN

= 0.948 fCLKIN

FOUT = fCLKIN/2

VIN = VREF/2

FOUT = fCLKIN/5

VIN = VREF/8

FOUT = fCLKIN ؋ 3/10

VIN = VREF/4

3t CLKIN

4t CLKIN

AVERAGE FOUT IS fCLKIN ؋ 3/10 BUT THE ACTUAL PULSE STREAM VARIES

BETWEEN fCLKIN/3 and fCLKIN/4

Figure 6. Frequency Output Waveforms

If there is a step change in input voltage, there is a settling time

that must elapse before valid data is obtained. This is typically

two CLKIN cycles.

REV. A

–7–

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