AD7801BR データシートの表示（PDF） - Analog Devices

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AD7801BR

+2.7 V to +5.5 V, Parallel Input,Voltage Output 8-Bit DAC

Analog Devices 

AD7801

Reference

The AD7801 has the ability to use either an external reference

applied through the REFIN pin or an internal reference generated

from VDD. Figure 20 shows the reference input arrangement

where either the internal VDD/2 or the externally applied reference

can be selected.

The internal reference is selected by tying the REFIN pin to

VDD. If an external reference is to be used, this can be directly

applied to the REFIN pin and if this is 1 V below VDD, the

internal circuitry will select this externally applied reference as

the reference source for the DAC.

Digital Interface

The AD7801 contains a fast parallel interface allowing this

DAC to interface to industry standard microprocessors,

microcontrollers and DSP machines. There are two modes in

which this parallel interface can be configured to update the

DAC output. The synchronous update mode allows synchro-

nous updating of the DAC output; the automatic update mode

allows the DAC to be updated individually following a write

cycle. Figure 21 shows the internal logic associated with the

digital interface. The PON STRB signal is internally generated

from the power-on reset circuitry and is low during the power-

on reset phase of the power up procedure.

CLR

PON STRB

LDAC

CS

WR

CLR

CLEAR

SET SLE

LDAC

DAC CONTROL

LOGIC

ENABLE

MLE

SLE

Figure 21. Logic Interface

The AD7801 has a double buffered interface, which allows for

synchronous updating of the DAC output. Figure 22 shows a

block diagram of the register arrangement within the AD7801.

4

15

15

30

DB7-DB0

8

UPPER

NIBBLE

4

15

15

30

LOWER

NIBBLE

CS

WR

LDAC

CLR

MLE

SLE

CONTROL LOGIC

Figure 22. Register Arrangement

Automatic Update Mode

In this mode of operation the LDAC signal is permanently tied

low. The state of the LDAC is sampled on the rising edge of

WR. LDAC being low allows the DAC register to be automati-

cally updated on the rising edge of WR. The output update

occurs on the rising edge of WR. Figure 23 shows the timing

associated with the automatic update mode of operation and

also the status of the various registers during this frame.

CS

WR

D7-D0

LDAC = 0

I/P REG (MLE)

DAC REG (SLE)

HOLD

TRACK

TRACK

HOLD

HOLD

TRACK

VOUT

Figure 23. Timing and Register Arrangement for Auto-

matic Update Mode

Synchronous Update Mode

In this mode of operation the LDAC signal is used to update the

DAC output to synchronize with other updates in the system.

The state of the LDAC is sampled on the rising edge of WR. If

LDAC is high, the automatic update mode is disabled and the

DAC latch is updated at any time after the write by taking

LDAC low. The output update occurs on the falling edge of

LDAC. LDAC must be taken back high again before the next

data transfer takes place. Figure 24 shows the timing associated

with the synchronous update mode of operation and also the

status of the various registers during this frame.

CS

WR

D7-D0

LDAC

I/P REG (MLE)

DAC REG (SLE)

HOLD

TRACK

HOLD

HOLD

TRACK

HOLD

VOUT

Figure 24. Timing and Register Arrangement for Synchro-

nous Update Mode

–8–

REV. 0

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