MXED102 データシートの表示（PDF） - Clare Inc => IXYS
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MXED102 Datasheet PDF : 20 Pages
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MXED102
Preliminary
Input Registers
Register Address 0 - Test Register
Eight bits of data can be written to and read from this register in order to test the serial port. This register
has no effect on the column driver.
Register Address 1 - Control Register 1
Bit(s)
7
Name
Freeze Master
6
Disable Precharge Driver
5
Standby
4
Short Channels
3
Color Mode
2
Data Mux
1-0 Test Mode(1:0)
Description
Modes:
1 => MASTER_OUT pin is not changed
0 => Normal, MASTER_OUT is updated to
MASTER_IN on rising edge of LE
Modes:
1 => Precharge circuit is disabled
0 => Normal
Modes:
1 => Part is operating normally
0 => Part is in low power standby mode
Modes:
1 => Channels are all shorted to ground after the
CLKEX count reaches 64
0 => Each channel is individually shorted to ground
after its current source is tristated
Modes:
0 => Monochrome mode
1 => Color mode
Modes:
0 => DA(5-0), DB(5-0), DC(5-0) data words are read
serially from the DC(5-0) pins. The DA(5-0) and
DB(5-0) pins are unused.
1 => DA(5-0), DB(5-0), DC(5-0) pins used to read
their respective data words.
Modes:
00 => Normal operation
01 => Test mode 1
10 => Test mode 2
11 => Test mode 3
Default
0
0
0
0
0
0
00
Register Address 2 - Control Register 2
Bit(s)
7-2
1
-
-
0
-
Name
Undefined
Fast Conversion
-
-
High A/D Gain
-
Description
-
Modes:
0 => Normal operation
1 =>
Modes:
0 => Normal operation
Default
-
-
0
-
-
0
6
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Rev. 2
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