MXED102 データシートの表示（PDF） - Clare Inc => IXYS

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MXED102

240-Channel OLED Column Driver

Clare Inc => IXYS 

Preliminary

Register Address 3 - A Output Group Data Current Magnitude Register

The 5 LSB bits determine the magnitude of A output group current during data output.

Register Address 4 - B Output Group Data Current Magnitude Register

The 5 LSB bits determine the magnitude of B output group current during data output.

Register Address 5 - C Output Group Data Current Magnitude Register

The 5 LSB bits determine the magnitude of C output group current during data output.

Register Address 6 - A Output Group Precharge Voltage Magnitude Register

The 8 bits determine the magnitude of A output group voltage during precharge.

Register Address 7 - B Output Group Precharge Voltage Magnitude Register

The 8 bits determine the magnitude of B output group voltage during precharge.

Register Address 8 - C Output Group Precharge Voltage Magnitude Register

The 8 bits determine the magnitude of C output group voltage during precharge.

Register Address 9 - Precharge Count Register

The 3 LSB bits set the precharge time to 0 to 7 CLKEX clock counts.

Register Address 10- A/D Converter Control Register

This register determines which signal is monitored by the A/D converter.

Bit(s)

Name

Description

7-4

UNDEFINED

-

3-0

ad_sel(3:0)

0xF => Measure VDDA ( Low Gain )

0xE => Measure TESTA ( Low Gain )

0xD => Measure IOUT231 ( Low Gain )

0xC => Measure IOUT6 ( Low Gain )

0xB=> Measure VDDB ( Low Gain )

0xA => Measure TESTB ( Low Gain )

0x9 => Measure IOUT232 ( Low Gain )

0x8 => Measure IOUT7 ( Low Gain )

0x7 => Measure VDDC ( Low Gain )

0x6 => Measure TESTC ( Low Gain )

0x5 => Measure IOUT233 ( Low Gain )

0x4 => Measure IOUT8 ( Low Gain )

0x3 - 0x2 => Undefined

0x1 => Measure AD_IN input ( High Gain )

0x0 => Input grounded

MXED102

Default

-

0000

Rev. 2

www.clare.com

7

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