AD7940BRMZ データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD7940BRMZ

3 mW, 100 kSPS, 14-Bit ADC in 6-Lead SOT-23

Analog Devices 

MICROPROCESSOR INTERFACING

The serial interface on the AD7940 allows the part to be directly

connected to a range of many different microprocessors. This

section explains how to interface the AD7940 with some of the

more common microcontroller and DSP serial interface

protocols.

AD7940 TO TMS320C541

The serial interface on the TMS320C541 uses a continuous

serial clock and frame synchronization signals to synchronize

the data transfer operations with peripheral devices such as the

AD7940. The CS input allows easy interfacing between the

TMS320C541 and the AD7940 with no glue logic required. The

serial port of the TMS320C541 is set up to operate in burst

mode with internal CLKX (TX serial clock) and FSX (TX frame

sync). The serial port control register (SPC) must have the

following setup:

FO = 0

FSM = 1

MCM = 1

TXM = 1

The format bit, FO, must be set to 1 to set the word length to

8 bits, in order to implement the power-down mode on the

AD7940. The connection diagram is shown in Figure 21. It

should be noted that for signal processing applications, it is

imperative that the frame synchronization signal from the

TMS320C541 provide equidistant sampling.

AD7940*

SCLK

SDATA

TMS320C541*

CLKX

CLKR

DR

CS

FSX

FSR

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 21. Interfacing to the TMS320C541

AD7940

AD7940 TO ADSP-218x

The ADSP-218x family of DSPs can be interfaced directly to the

AD7940 with no glue logic required. The SPORT control regis-

ter should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 1111, 16-Bit Data-Words

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 0, Frame First Word

IRFS = 0

ITFS = 1

To implement power-down mode, SLEN should be set to 0111

to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 22. The ADSP-218x

has the TFS and RFS of the SPORT tied together, with TFS set

as an output and RFS set as an input. The DSP operates in

alternate framing mode, and the SPORT control register is set

up as described. The frame synchronization signal generated on

the TFS is tied to CS, and, as with all signal processing

applications, equidistant sampling is necessary. In this example,

the timer interrupt is used to control the sampling rate of the

ADC.

AD7940*

SCLK

SDATA

CS

ADSP-218x*

SCLK

DR

RFS

TFS

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 22. Interfacing to the ADSP-218x

The timer register is loaded with a value that provides an

interrupt at the required sample interval. When an interrupt is

received, the values in the transmit autobuffer start to be

transmitted and TFS is generated. The TFS is used to control

the

RFS and, therefore, the reading of data. The data is stored in the

receive autobuffer for processing or to be shifted later. The

frequency of the serial clock is set in the SCLKDIV register.

When the instruction to transmit with TFS is given, i.e., TX0 =

AX0, the state of the SCLK is checked. The DSP waits until the

SCLK has gone high, low, and high before transmission will

start. If the timer and SCLK values are chosen such that the

instruction to transmit occurs on or near the rising edge of

SCLK, the data may be transmitted, or it may wait until the next

clock edge.

Rev. A | Page 17 of 20

Share Link: