AD7945BR データシートの表示（PDF） - Analog Devices

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AD7945BR

+3.3 V/+5 V Multiplying 12-Bit DACs

Analog Devices 

AD7943/AD7945/AD7948

AD7943 TIMING SPECIFICATIONS1 (TA = TMIN to TMAX, unless otherwise noted)

Parameter

tSTB2

tDS

tDH

tSRI

tLD

tCLR

tASB

tSV3

Limit @

VDD = +3 V to +3.6 V

60

15

35

55

55

55

0

60

Limit @

VDD = +4.5 V to +5.5 V

40

10

25

35

35

35

0

35

Units

ns min

ns min

ns min

ns min

ns min

ns min

ns min

ns max

Description

STB Pulsewidth

Data Setup Time

Data Hold Time

SRI Data Pulsewidth

Load Pulsewidth

CLR Pulsewidth

Min Time Between Strobing Input Shift

Register and Loading DAC Register

STB Clocking Edge to SRO Data Valid Delay

NOTES

1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 µs on any digital input.

2STB mark/space ratio range is 60/40 to 40/60.

3tSV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.

Specifications subject to change without notice.

STB1,

STB2,

STB4

tSTB

STB3

SRI

tDH

t DS

tSRI

DB11(N)

(MSB)

LD1,

LD2,

CLR

SRO

DB10(N)

t SV

DB10(N–1)

Figure 1. AD7943 Timing Diagram

DB0(N)

tASB

tLD, tCLR

DB0(N–1)

1.6mA IOL

TO OUTPUT

PIN

CL

50pF

200␮A IOH

+2.1V

Figure 2. Load Circuit for Digital Output Timing Specifications

REV. B

–5–

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