AD7947 データシートの表示（PDF） - Analog Devices
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AD7947 Datasheet PDF : 20 Pages
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AD7940
TIMING SPECIFICATIONS
Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from
a voltage level of 1.6 V.
VDD = 2.50 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
fSCLK1
tCONVERT
tQUIET
Limit at TMIN, TMAX
3V
5V
250
250
2.5
2.5
16 × tSCLK
16 × tSCLK
50
50
Unit
kHz min
MHz max
min
ns min
t1
t2
t32
t42
t5
t6
t7
t83
tPOWER-UP4
10
10
48
120
0.4 tSCLK
0.4 tSCLK
10
45
1
10
10
35
80
0.4 tSCLK
0.4 tSCLK
10
35
1
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
µs typ
Description
Minimum quiet time required between bus relinquish and start of
next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
Power up time from full power-down
1 Mark/space ratio for the SCLK input is 40/60 to 60/40.
2 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
3 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
4 See the Power vs. Throughput Rate section.
200µA
IOL
TO OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specification
Rev. 0 | Page 5 of 20
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