AD8139(RevB) データシートの表示（PDF） - Analog Devices

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AD8139
(Rev.:RevB)

Low Noise, Rail-to-Rail, Differential ADC Driver

Analog Devices 

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

Supply Voltage

VOCM

Power Dissipation

Input Common-Mode Voltage

Storage Temperature Range

Operating Temperature Range

Lead Temperature (Soldering 10 sec)

Junction Temperature

Rating

12 V

±VS

See Figure 4

±VS

−65°C to +125°C

−40°C to +125°C

300°C

150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is

specified for device soldered in circuit board for surface-mount

packages.

Table 4.

Package Type

8-Lead SOIC with EP/4-Layer

8-Lead LFCSP/4-Layer

θJA

Unit

70

°C/W

70

°C/W

Maximum Power Dissipation

The maximum safe power dissipation in the AD8139 package

is limited by the associated rise in junction temperature (TJ) on

the die. At approximately 150°C, which is the glass transition

temperature, the plastic will change its properties. Even

temporarily exceeding this temperature limit can change the

stresses that the package exerts on the die, permanently shifting

the parametric performance of the AD8139. Exceeding a junction

temperature of 175°C for an extended period can result in

changes in the silicon devices potentially causing failure.

AD8139

The power dissipated in the package (PD) is the sum of the

quiescent power dissipation and the power dissipated in the

package due to the load drive for all outputs. The quiescent

power is the voltage between the supply pins (VS) times the

quiescent current (IS). The load current consists of differential

and common-mode currents flowing to the load, as well as

currents flowing through the external feedback networks and

the internal common-mode feedback loop. The internal resistor

tap used in the common-mode feedback loop places a 1 kΩ

differential load on the output. RMS output voltages should be

considered when dealing with ac signals.

Airflow reduces θJA. In addition, more metal directly in contact

with the package leads from metal traces, through holes,

ground, and power planes reduce the θJA.

Figure 4 shows the maximum safe power dissipation in the

package vs. the ambient temperature for the exposed paddle

(EP) 8-lead SOIC (θJA = 70°C/W) and the 8-lead LFCSP

(θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA values

are approximations.

4.0

3.5

3.0

2.5

2.0

1.5

SOIC

AND LFCSP

1.0

0.5

0

–40 –20

0

20 40 60 80

AMBIENT TEMPERATURE (°C)

100 120

Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

Rev. B | Page 7 of 24

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