AD8381(Rev0) データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD8381
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD8381 Datasheet PDF : 16 Pages
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AD8381
Pin No.
Mnemonic
1, 12, 19, 23, NC
24, 43–45
2–11
DB (0:9)
13
E/O
14
R/L
15
INV
16
17
18, 27, 31,
35, 42
20
DGND
DVCC
AVCCx
STBY
21
BYP
22, 25, 29,
33, 37, 41
26, 28, 30,
32, 34, 36
38
AGNDx
VID5, VID4, VID3,
VID2, VID1, VID0
VMID
39
VREFLO
40
VREFHI
46
STSQ
47
XFR
48
CLK
PIN FUNCTION DESCRIPTIONS
Function
No Connect
Description
Data Input
Even/Odd Select
Right/Left Select
Invert
Digital Supply Return
Digital Power Supply
Analog Power Supplies
10-Bit Data Input MSB = DB (9).
The active CLK edge is the rising edge when this input is held HIGH
and it is the falling edge when this input is held LOW.
Data is loaded sequentially on the rising edges of CLK when this input
is HIGH and loaded on the falling edges when this input is LOW.
A new data loading sequence begins on the left, with Channel 0, when this
input is LOW, and on the right, with Channel 5 when this input is HIGH.
When this pin is HIGH, the analog output voltages are above VMID.
When LOW, the analog output voltages are below VMID.
This pin is normally connected to the analog ground plane.
Digital Power Supply.
Analog Power Supplies.
Standby
Bypass
Analog Supply Returns
When HIGH, the internal circuits are “debiased” and the power
dissipation drops to a minimum.
A 0.1 µF capacitor connected between this pin and AGND ensures
optimum settling time.
These pins are normally connected to the analog ground plane.
Analog Outputs
These pins are directly connected to the analog inputs of the LCD panel.
Midpoint Reference
Full-Scale Reference
Full-Scale Reference
Start Sequence
Data Transfer
Clock
The voltage applied between this pin and AGND sets the midpoint
reference of the analog outputs. This pin is normally connected to VCOM.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
A new data loading sequence begins on the rising edge of CLK when
this input was HIGH on the preceding rising edge of CLK and the E/O
input is held HIGH.
A new data loading sequence begins on the falling edge of CLK when
this input was HIGH on the preceding falling edge of CLK and the E/O
input is held LOW.
Data is transferred to the outputs on the immediately following falling
edge of CLK when this input is HIGH on the rising edge of CLK.
Clock Input.
PIN CONFIGURATION
REV. 0
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
DB0 2
DB1 3
DB2 4
DB3 5
DB4 6
DB5 7
DB6 8
DB7 9
DB8 10
DB9 11
NC 12
PIN 1
IDENTIFIER
AD8381
TOP VIEW
(Not to Scale)
36 VID0
35 AVCC0, 1
34 VID1
33 AGND1, 2
32 VID2
31 AVCC2, 3
30 VID3
29 AGND3, 4
28 VID4
27 AVCC4, 5
26 VID5
25 AGND5
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
–5–
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