AD8339 データシートの表示（PDF） - Analog Devices

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AD8339

DC to 50 MHz, Quad I/Q Demodulator and Phase Shifter

Analog Devices 

AD8339

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Preliminary Technical Data

RF2N 1

RF2P 2

COMM 3

COMM 4

SCLK 5

CSB 6

VPOS 7

VPOS 8

RF3P 9

RF3N 10

Pin 1

Identifier

AD8339

Top View

(not to scale)

30 Q2OP

29 I2OP

28 VPOS

27 VPOS

26 4LOP

25 4LON

24 VNEG

23 VNEG

22 I3OP

21 Q3OP

Figure 2. 40-Lead LFCSP

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2, 9, 10,

13, 14, 37,

38

RF1P-RF4P

RF1N-RF4N

RF Inputs. No internal bias. The optimum common mode voltage for maximum symmetrical input differential

swing is 2.5 V if ±5 V supplies are used.

3, 4, 15, 36 COMM

Ground

5

SCLK

Serial Interface – Clock

6

CSB

Serial Interface – Chip Select Bar. Active Low.

7, 8, 11,

16, 27, 28,

35

VPOS

Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF

and 1 nF capacitor between the VPOS pins and ground. Since the VPOS pins are internally connected, one set

of supply decoupling components on each side of the chip should be sufficient.

12

SDO

Serial Interface – Data Output. Normally connected to SDI of next chip or left open.

17

LODC

Decoupling Pin for LO. A 0.1 μF capacitor should be connected between this pin and ground. Value of cap

does influence chip enable/disable times.

18, 19, 21,

22, 29, 30,

32, 33

I1OP-I4OP,

Q1OP-Q4OP

I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a

transimpedance amplifier. Multiple outputs can be summed together through simply connecting them

(Wire-OR). The bias voltage should be set to 0 V or less by the transimpedance amplifier, see Figure 7.

20, 23, 24, VNEG

31

Negative Supply. These pin should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF

and 1 nF capacitor between the pin and ground. Since the VNEG pins are internally connected, one set of

supply decoupling components should be sufficient.

25, 26

4LOP, 4LON LO Inputs. No internal bias; optimally biased by an LVDS driver. For best performance, these inputs should be

driven differentially.

34

RSET

LO Interface - Reset. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS logic.

39

SDI

Serial Interface – Data Input. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS

logic.

40

RSTS

Reset for SPI Interface. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS logic. For

quick testing without the need to program the SPI, the voltage on the RSTS pin should be pulled to -1.4 V;

this enables all four channels in the Phase (I=1,Q=0) state.

Rev. PrA | Page 6 of 15

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