AD8384 データシートの表示（PDF） - Analog Devices
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AD8384 Datasheet PDF : 24 Pages
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AD8384
TIMING CHARACTERISTICS
DECDRIVER SECTION
10
DB(0:9)
10 10 2-STAGE 10 DAC
LATCH
AD8384
10 2-STAGE 10 DAC
LATCH
BYP
CLK
STSQ
XFR
R/L
BIAS
SEQUENCE
CONTROL
10 2-STAGE 10 DAC
LATCH
10 2-STAGE 10 DAC
LATCH
10 2-STAGE 10 DAC
LATCH
10 2-STAGE 10 DAC
LATCH
INV
INV CONTROL
SCALING
CONTROL
VRH VRL
V1 V2
Figure 4. Block Diagram
VID0
VID1
VID2
VID3
VID4
VID5
tf
CLK
DB(0:9)
tr
t1
t7
t2
t8
VTH
VTH
STSQ
XFR
CLK
DB(0:9)
VTH
t3
t4
VTH
t5
t6
Figure 5. Input Timing, Even Mode (E/O = HIGH)
t8
t1
t2
t7
VTH
VTH
STSQ
VTH
t3
t4
XFR
VTH
t5
t6
Figure 6. Input Timing, Odd Mode ( E/O = LOW)
CLK
DB(0:9) –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7
STSQ
XFR
INV
V2+VFS
VID(0:5)
V2
50%
t9
50% PIXELS
–6, –5, –4, –3, –2, –1
t9
PIXELS 0, 1, 2, 3, 4, 5
t10
V1
V1–VFS
Figure 7. Output Timing (R/L = Low, E/O = High)
Table 8. Timing Characteristics
Parameter
t1
CLK to Data Setup Time
t2
CLK to Data Hold Time
t3
CLK to STSQ Setup Time
t4
CLK to STSQ Hold Time
t5
CLK to XFR Setup Time
t6
CLK to XFR Hold Time
t7
CLK High Time
t8
CLK Low Time
t9
CLK to VIDx Delay
t10
INV to VIDx Delay
Conditions
Min Typ
0
3
0
3
0
3
3
2.5
10
12
13
15
Max
14
17
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 11 of 24
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