AD9139(Rev0) データシートの表示（PDF） - Analog Devices
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AD9139 Datasheet PDF : 56 Pages
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Data Sheet
AD9139
tH
tS
INPUT DATA
DCI
DATA SAMPLE CLOCK
tDCI SKEW
INPUT DATA
DCI
DATA EYE
tDATA PERIOD
tDATA JITTER
DLL
PHASE
DELAY
tH + tS tDATA JITTER
DATA EYE
tDATA PERIOD
DATA SAMPLE CLOCK
Figure 30. LVDS Data Port Timing Requirements
Figure 30 shows that the ideal location for the DSC signal is 90°
out of phase from the DCI input; however, due to skew of the
DCI relative to the data, it may be necessary to change the DSC
phase offset to sample the data at the center of its eye diagram.
Vary the sampling instance in discrete increments by offsetting the
nominal DLL phase shift value of 90° via Register 0x0A, Bits[3:0].
This register is a signed value. The MSB is the sign and the LSBs
are the magnitude. The following equation defines the phase
offset relationship:
Phase Offset = 90° + n × 11.25°, |n| < 7
where n is the DLL phase offset setting.
Figure 31 shows the DSC setup and hold times with respect to
the DCI signal and data signals.
DATA
DCI
Table 12 lists the guaranteed values across the operating condi-
tions. These values were obtained using a 50% duty cycle and a
DCI swing of 450 mV p-p. For best performance, maintain a
duty cycle variation below ±5% and set the DCI input as high as
possible, up to 1200 mV p-p.
Table 12. DLL Phase Setup and Hold Times (Guaranteed)
Frequency,
fDCI (MHz)
Time (ps)
Data Port Setup and Hold Times (ps)
at DLL Phase
−3
0
+3
307
tS
−125
−385
−695
tH
834
1120
1417
368
tS
−70
−305
−534
tH
753
967
1207
491
tS
−81
−245
−402
tH
601
762
928
614
tS
−54.0
−167
−277
tH
497
603
721
DSC
tS
tH
Figure 31. LVDS Data Port Setup and Hold Times
Rev. 0 | Page 19 of 56
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