AD9139(Rev0) データシートの表示（PDF） - Analog Devices
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AD9139 Datasheet PDF : 56 Pages
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Data Sheet
AD9139
DLL Configuration Example 1
In the following DLL configuration example, fDCI = 600 MHz,
DLL is enabled, and DLL phase offset = 0.
1. 0x5E → 0xFE /* Turn off LSB delay cell*/
2. 0x0D → 0x06 /* Select DLL configure
options */
3. 0x0A → 0xC0 /* Enable DLL and duty cycle
correction. Set DLL phase offset to 0 */
4. Read 0x0E[7:4] /* Expect 1000b if the DLL
is locked */
DLL Configuration Example 2
In the following DLL configuration example, fDCI = 300 MHz,
DLL is enable, and DLL phase offset = 0.
1. 0x5E → 0xFE /* Turn off LSB delay cell*/
2. 0x0D → 0x86 /* Select DLL configure
options */
3. 0x0A → 0xC0 /* Enable DLL and duty cycle
correction. Set DLL phase offset to 0 */
4. Read 0x0E[7:4] /* Expect 1000b if the DLL
is locked */
PARITY
The data interface can be continuously monitored by enabling
the parity bit feature in Register 0x6A[7] and configuring the
frame/parity bit as parity by setting Register 0x09 = 0x21. In
this case, the host sends a parity bit with each data sample. This
bit is set according to the following formulas, where n is the
data sample that is being checked:
samples, as well as configures the AD9139 to generate an IRQ.
The user can then sweep the sampling instance of the input
registers of the AD9139 to determine at what point sampling
errors occur. The sampling instance can be varied in discrete
increments by offsetting the nominal DLL phase shift value of
90° via SPI Register 0x0A[3:0].
SED OPERATION
The AD9139 provides on-chip sample error detection (SED)
circuitry that simplifies verification of the input data interface.
The SED compares the input data samples captured at the digital
input pins with a set of comparison values. The comparison values
are loaded into registers through the SPI port. Differences between
the captured values and the comparison values are detected.
Options are available for customizing SED test sequencing and
error handling.
The SED circuitry allows the application to test a short user
defined pattern to confirm that the high speed source
synchronous data bus is correctly implemented and meets the
timing requirement. Unlike the parity bit, the SED circuitry is
expected to be used during initial system calibration, before the
AD9139 is in use in the application. The SED circuitry operates
on a data set made up of user defined input words, denoted as
S0, S1, S2, and S3. The user defined pattern consists of
sequential data-word samples (S0 is sampled on the rising edge
of DCI, S1 is sampled on the following falling edge of DCI, S2 is
sampled on the following DCI rising edge, and S3 is sampled on
the following DCI falling edge). The user loads this data pattern
in the byte format into Register 0x61 through Register 0x68.
For even parity,
XOR[FRM(n), D0(n), D1(n), D2(n), …, D15(n)] = 0
For odd parity,
XOR[FRM(n), D0(n), D1(n), D2(n), …, D15(n)] = 1
The parity bit is calculated over 17 bits (including the
frame/parity bit).
If a parity error occurs, the parity error counter (Register 0x6B
or Register 0x6C) increments. Parity errors on the bits sampled
by the rising edge of the DCI signal increment the rising edge
parity counter (Register 0x6B) and set the PARERRRIS bit
(Register 0x6A[0]). Parity errors on the bits sampled by the
falling edge of DCI increment the falling edge parity counter
(Register 0x6C) and set the PARERRFAL bit (Register 0x6A[1]).
The parity counter continues to accumulate until it clears or
until it reaches a maximum value of 255. To clear the count,
write a 1 to Register 0x6A[5].
To trigger an IRQ when a parity error occurs, write 1 to Bit 7 in
Register 0x04. This IRQ triggers when there is either a rising
edge or falling edge parity error. Observe the status of the IRQ
pin via Register 0x06[7] or by using the selected IRQx pin. Clear
the IRQ by writing a 1 to Register 0x06[7].
Use the parity bit feature to validate the interface timing. As
described previously, the host provides a parity bit with the data
The depth of the user defined pattern is selectable via Bit 4 of
the SED_CTRL register (0x60). A default of 0, means a depth of
two (using S0 and S1), and a 1 means a depth of four (using S0,
S1, S2, and S3, and requiring the use of frame signal input to
define S0 to the SED state machine). To properly align the input
samples using a depth of 4, S0 is indicated by asserting the
frame signal for a minimum of two complete input samples as
shown in. The frame signal can be issued once at the start of the
data transmission, or it can be asserted repeatedly at intervals
coinciding with the S0 word.
FRAME
DATA[15:0]
S0
S1
S2
S3
S0
S1
Figure 32. Timing Diagram of Extended FRAMEx Signal Required to Align
Input Data for SED
The SED has three flag bits (Register 0x60, Bit 0, Bit 1, and
Bit 2) that indicate the results of the input sample comparisons.
The sample error detected bit (Register 0x60, Bit 0) is set when
an error is detected and remains set until cleared.
The autosample error detection (AED) mode is an autoclear
mode that has two effects: it activates the compare fail bit and
the compare pass bit (Register 0x60, Bit 1 and Bit 2). The
compare pass bit sets if the last comparison indicated the
sample was error free. The compare fail bit sets if an error is
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