AD9139(Rev0) データシートの表示（PDF） - Analog Devices

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AD9139
(Rev.:Rev0)

16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

Data Sheet

PLL Control Register ..................................................................46

PLL Control Register ..................................................................47

PLL Control Register ..................................................................47

PLL Status Register .....................................................................47

PLL Status Register .....................................................................48

DAC FS Adjust LSB Register .....................................................48

DAC FS Adjust MSB Register....................................................48

Die Temperature Sensor Control Register...............................48

Die Temperature LSB Register ..................................................48

Die Temperature MSB Register.................................................49

Chip ID Register..........................................................................49

Interrupt Configuration Register..............................................49

Sync CTRL Register ....................................................................49

Frame Reset CTRL Register.......................................................49

FIFO Level Configuration Register ..........................................50

FIFO Level Readback Register ..................................................50

FIFO CTRL Register...................................................................50

Data Format Select Register.......................................................51

Datapath Control Register .........................................................51

Interpolation Control Register ..................................................51

Power-Down Data Input 0 Register..........................................51

DAC_DC_OFFSET0 Register ...................................................51

DAC_DC_OFFSET1 Register ...................................................51

DAC_GAIN_ADJ Register ........................................................52

REVISION HISTORY

10/13—Revision 0: Initial Version

AD9139

Gain Step Control0 Register ......................................................52

Gain Step Control1 Register ......................................................52

TX Enable Control Register ......................................................52

DAC Output Control Register ..................................................53

DLL Cell Enable 0 Register........................................................53

DLL Cell Enable 1 Register........................................................53

SED Control Register .................................................................53

SED Pattern S0 Low Bits Register .............................................54

SED Pattern S0 High Bits Register............................................54

SED Pattern S1 Low Bits Register .............................................54

SED Pattern S1 High Bits Register............................................54

SED Pattern S2 Low Bits Register .............................................54

SED Pattern S2 High Bits Register............................................54

SED Pattern S3 Low Bits Register .............................................54

SED Pattern S3 High Bits Register............................................55

Parity Control Register...............................................................55

Parity Error Rising Edge Register .............................................55

Parity Error Falling Edge Register ............................................55

Version Register ..........................................................................55

Packaging and Ordering Information ..........................................56

Outline Dimensions ...................................................................56

Ordering Guide ...........................................................................56

Rev. 0 | Page 3 of 56

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