AD9139(Rev0) データシートの表示（PDF） - Analog Devices

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AD9139
(Rev.:Rev0)

16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

Data Sheet

AD9139

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.

Table 2.

Parameter

CMOS INPUT LOGIC LEVEL

Input

Logic High

Logic Low

CMOS OUTPUT LOGIC LEVEL

Output

Logic High

Logic Low

LVDS RECEIVER INPUTS

Input Voltage Range

Input Differential Threshold

Input Differential Hysteresis

Receiver Differential Input Impedance

DLL SPEED RANGE

DAC UPDATE RATE

DAC Adjusted Update Rate

DAC CLOCK INPUT (DACCLKP, DACCLKN)

Differential Peak-to-Peak Voltage

Common-Mode Voltage

REFCLK/SYNCCLK INPUT (REFP/SYNCP,

REFN/SYNCN)

Differential Peak-to-Peak Voltage

Common-Mode Voltage

Input Clock Frequency

SERIAL PORT INTERFACE

Maximum Clock Rate

Minimum Pulse Width

High

Low

SDIO to SCLK Setup Time

SDIO to SCLK Hold Time

CS to SCLK Setup Time

CS to SCLK Hold Time

SDIO to SCLK Delay

SDIO High-Z to CS

SDIO LOGIC LEVEL

Voltage Input High

Voltage Input Low

Voltage Output High

Voltage Output Low

Symbol

Test Conditions/Comments Min Typ Max

Unit

DVDD18 = 1.8 V

DVDD18 = 1.8 V

1.2

V

0.6

V

VIA or VIB

VIDTH

VIDTHH to VIDTHL

RIN

DVDD18 = 1.8 V

DVDD18 = 1.8 V

Data and frame inputs

1× interpolation

2× interpolation

Self biased input, ac-coupled

1.4

0.4

825

1675

−175

+175

20

100

250

575

1600

1150

800

100 500 2000

1.25

V

V

mV

mV

mV

Ω

MHz

MSPS

MSPS

MSPS

mV

V

SCLK

tPWH

tPWL

tDS

tDH

tDCSB

tDCSB

tDV

VIH

VIL

IIH

IIL

1.03 GHz ≤ fVCO ≤ 2.07 GHz

100 500 2000

mV

1.25

V

450

MHz

40

MHz

12.5

ns

12.5

ns

1.5

ns

0.68

ns

2.38 1.4

ns

9.6

ns

Wait time for valid output from 11

ns

SDIO

Time for SDIO to relinquish the 8.5

ns

output bus

With 2 mA loading

With 2 mA loading

1.2 1.8

V

0 0.5

V

1.36

2

V

0

0.45

V

Rev. 0 | Page 5 of 56

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