AD9235BRU-20(RevB) データシートの表示（PDF） - Analog Devices
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AD9235BRU-20 Datasheet PDF : 32 Pages
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DIGITAL SPECIFICATIONS
Parameter
Test AD9235BRU-20
Temp Level Min Typ Max
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Full IV
2.0
Full IV
0.8
Full IV
–10
+10
Full IV
–10
+10
Full V
2
LOGIC OUTPUTS*
DRVDD = 3.3 V
High-Level Output Voltage
Full IV
3.29
(IOH = 50 µA)
High-Level Output Voltage
Full IV
3.25
(IOH = 0.5 mA)
Low-Level Output Voltage
Full IV
0.2
(IOL = 1.6 mA)
Low-Level Output Voltage
Full IV
0.05
(IOL = 50 µA)
DRVDD = 2.5 V
High-Level Output Voltage
Full IV
2.49
(IOH = 50 µA)
High-Level Output Voltage
Full IV
2.45
(IOH = 0.5 mA)
Low-Level Output Voltage
Full IV
0.2
(IOL = 1.6 mA)
Low-Level Output Voltage
Full IV
0.05
(IOL = 50 µA)
*Output voltage levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
AD9235
AD9235BRU-40 AD9235BRU/BCP-65
Min Typ Max Min Typ Max Unit
2.0
–10
–10
2
2.0
0.8
+10 –10
+10 –10
2
V
0.8 V
+10 µA
+10 µA
pF
3.29
3.29
V
3.25
3.25
V
0.2
0.2 V
0.05
0.05 V
2.49
2.49
V
2.45
2.45
V
0.2
0.2 V
0.05
0.05 V
Parameter
Test AD9235BRU-20
AD9235BRU-40 AD9235BRU/BCP-65
Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full VI
20
Minimum Conversion Rate
Full V
CLK Period
Full V
50.0
CLK Pulsewidth High1
CLK Pulsewidth Low1
Full V
15.0
Full V
15.0
40
1
25.0
8.8
8.8
65
1
15.4
6.2
6.2
MSPS
1
MSPS
ns
ns
ns
DATA OUTPUT PARAMETERS
Output Delay2 (tPD)
Full V
3.5
3.5
3.5
ns
Pipeline Delay (Latency)
Full V
7
7
7
Cycles
Aperture Delay (tA)
Full V
1.0
1.0
1.0
ns
Aperture Uncertainty Jitter (tJ) Full V
0.5
0.5
0.5
ps rms
Wake-Up Time3
Full V
3.0
3.0
3.0
ms
OUT-OF-RANGE RECOVERY
TIME
Full V
1
1
2
Cycles
NOTES
1For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.
2Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
ANALOG
INPUT
N N+1
N+2
N+8
N–1
tA
N+3
N+4
N+7
N+5 N+6
REV. B
CLK
DATA
OUT
N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1
N
tPD
=
6.0ns MAX
2.0ns MIN
Figure 1. Timing Diagram
–3–
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