AD9235BCPZRL7-65 データシートの表示（PDF） - Analog Devices
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AD9235BCPZRL7-65 Datasheet PDF : 41 Pages
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Data Sheet
AD9235
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, TMIN to TMAX,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input4
Sine Wave Input2
Standby Power5
Temp
Full
Test
Level
VI
AD9235BRU/BCP-20
Min Typ Max
12
Full VI
Full VI
Full VI
Full IV
25°C I
Full IV
25°C I
12
±0.30 ±1.20
±0.30 ±2.40
±0.35 ±0.65
±0.35
±0.45 ±0.80
±0.40
Full V
±2
Full V
±12
Full VI
Full V
Full V
Full V
±5 ±35
0.8
±2.5
0.1
25°C V
0.54
25°C V
0.27
Full IV
1
Full IV
2
Full V
7
Full V
7
Full IV
Full IV
Full V
Full V
Full V
Full V
Full VI
Full V
2.7 3.0 3.6
2.25 3.0 3.6
30
2
±0.01
90
95
110
1.0
AD9235BRU/BCP-40
Min Typ Max
12
12
±0.50 ±1.20
±0.50 ±2.50
±0.35 ±0.75
±0.35
±0.50 ±0.90
±0.40
±2
±12
±5 ±35
0.8
±2.5
0.1
0.54
0.27
1
2
7
7
2.7 3.0 3.6
2.25 3.0 3.6
55
5
±0.01
165
180 205
1.0
AD9235BRU/BCP-65
Min Typ Max
12
12
±0.50 ±1.20
±0.50 ±2.60
±0.40 ±0.80
±0.35
±0.70 ±1.30
±0.45
±3
±12
±5 ±35
0.8
±2.5
0.1
0.54
0.27
1
2
7
7
2.7 3.0 3.6
2.25 3.0 3.6
100
7
±0.01
300
320 350
1.0
Unit
Bits
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
kΩ
V
V
mA
mA
% FSR
mW
mW
mW
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.
4 Measured with dc input at maximum clock rate.
5 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
Rev. D | Page 3 of 40
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