AD9236BRURL7-80 データシートの表示（PDF） - Analog Devices

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AD9236BRURL7-80

12-Bit, 80 MSPS, 3 V A/D Converter

Analog Devices 

AD9236

SWITCHING SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

Parameter

CLOCK INPUT PARAMETERS

Maximum Conversion Rate

Minimum Conversion Rate

CLK Period

CLK Pulse Width High1

CLK Pulse Width Low1

DATA OUTPUT PARAMETERS

Output Propagation Delay (tPD)2

Pipeline Delay (Latency)

Aperture Delay (tA)

Aperture Uncertainty (Jitter, tJ)

Wake-Up Time3

OUT OF RANGE RECOVERY TIME

Temp

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Test Level Min

VI

80

V

V

12.5

V

4.0

V

4.0

V

V

V

V

V

V

AD9236BRU/AD9236BCP

Typ

Max

1

3.5

7

1.0

0.3

7

2

Unit

MSPS

MSPS

ns

ns

ns

ns

Cycles

ns

ps rms

ms

Cycles

1 With duty cycle stabilizer (DCS) enabled.

2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3 Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.

ANALOG

INPUT

N

N+1

N+2

N+8

N–1

tA

N+3

N+4

N+7

N+5 N+6

CLK

DATA

OUT

N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1

tPD = 6.0ns MAX

2.0ns MIN

Figure 2. Timing Diagram

N

03066-0-002

Table 5. Explanation of Test Levels

Test Level Definitions

I

100% production tested.

II

100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

III

Sample tested only.

IV

Parameter is guaranteed by design and characterization testing.

V

Parameter is a typical value only.

VI

100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

Rev. B | Page 6 of 36

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