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AD9238BST-65(RevA) データシートの表示(PDF) - Analog Devices

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AD9238BST-65
(Rev.:RevA)
ADI
Analog Devices ADI
AD9238BST-65 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9238
DC SPECIFICATIONS (continued)
Parameter
Test AD9238BST-20
Temp Level Min Typ Max
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Full IV 2.0
Full IV
0.8
Full IV –10
+10
Full IV –10
+10
Full V
2
LOGIC OUTPUTS*
DRVDD = 3.3 V
High Level Output Voltage
Full IV 3.29
(IOH = 50 mA)
High Level Output Voltage
Full IV 3.25
(IOH = 0.5 mA)
Low Level Output Voltage
Full IV
0.05
(IOL = 50 mA)
Low Level Output Voltage
Full IV
0.2
(IOL = 1.6 mA)
DRVDD = 2.5 V
High Level Output Voltage
Full IV 2.49
(IOH = 50 mA)
High Level Output Voltage
Full IV 2.45
(IOH = 0.5 mA)
Low Level Output Voltage
Full IV
0.05
(IOL = 50 mA)
Low Level Output Voltage
Full IV
0.2
(IOL = 1.6 mA)
*Output Voltage Levels measured with 5 pF load on each output.
Specifications subject to change without notice.
AD9238BST-40
Min Typ Max
2.0
0.8
–10
+10
–10
+10
2
3.29
3.25
0.05
0.2
2.49
2.45
0.05
0.2
AD9238BST-65
Min Typ Max Unit
2.0
–10
–10
2
V
0.8 V
+10 µA
+10 µA
pF
3.29
V
3.25
V
0.05 V
0.2 V
2.49
V
2.45
V
0.05 V
0.2 V
SWITCHING SPECIFICATIONS
Parameter
Test AD9238BST-20
AD9238BST-40
AD9238BST-65
Temp Level Min Typ Max Min Typ Max Min Typ Max
SWITCHING PERFORMANCE
Max Conversion Rate
Full VI 20
Min Conversion Rate
Full V
CLK Period
CLK Pulsewidth High1
Full V 50.0
Full V 15.0
CLK Pulsewidth Low1
Full V 15.0
40
1
25.0
8.8
8.8
65
1
1
15.4
6.2
6.2
DATA OUTPUT PARAMETERS
Output Delay2 (tPD)
Pipeline Delay (Latency)
Full IV 2
3.5 6
2
3.5 6
Full V
7
7
Aperture Delay (tA)
Full V
1.0
1.0
Aperture Uncertainty (tJ)
Full V
0.5
0.5
Wake-Up Time3
Full V
2.5
2.5
2 3.5 6
7
1.0
0.5
2.5
OUT-OF-RANGE RECOVERY TIME Full V
1
1
2
NOTES
1The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC 20).
2Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output.
3Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
ms
Cycles
REV. A
–3–

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