AD9268 データシートの表示（PDF） - Analog Devices
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AD9268 Datasheet PDF : 44 Pages
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AD9268
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-
by-8 Mode
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)2
DCO to Data Skew (tSKEW)
LVDS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)2
DCO to Data Skew (tSKEW)
CMOS Mode Pipeline Delay
(Latency)
LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B
Wake-Up Time3
Out-of-Range Recovery Time
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9268BCPZ-80
Min Typ
Max
625
20
80
10
80
12.5
3.75 6.25
8.75
5.95 6.25
6.55
0.8
1.0
0.07
2.8 3.5
4.2
3.1
−0.6 −0.4 0
2.9 3.7
4.5
3.9
−0.1 +0.2 +0.5
12
12/12.5
500
2
AD9268BCPZ-105
Min Typ
Max
625
20
105
10
105
9.5
2.85 4.75
6.65
4.5 4.75
5.0
0.8
1.0
0.07
2.8 3.5
4.2
3.1
−0.6 −0.4 0
2.9 3.7
4.5
3.9
−0.1 +0.2 +0.5
12
12/12.5
500
2
AD9268BCPZ-125
Min Typ
Max
625
20
125
10
125
8
2.4 4
5.6
3.8 4
4.2
0.8
1.0
0.07
2.8 3.5
4.2
3.1
−0.6 −0.4 0
2.9 3.7
4.5
3.9
−0.1 +0.2 +0.5
12
12/12.5
500
2
Unit
MHz
MSPS
MSPS
ns
ns
ns
ns
ns
ps
rms
ns
ns
ns
ns
ns
ns
Cycles
Cycles
μs
Cycles
1 Conversion rate is the clock rate after the divider.
2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
3 Wake-up time is defined as the time required to return to normal operation from power-down mode.
Rev. A | Page 9 of 44
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