AD9381 データシートの表示（PDF） - Analog Devices

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AD9381

HDMI™ Display Interface

Analog Devices 

AD9381

Pin Type

REFERENCES

POWER SUPPLY

CONTROL

HDCP

AUDIO DATA OUTPUTS

DATA ENABLE

RTERM

Pin No.

57

80, 76, 72, 67,

45, 33

100, 90, 10

59, 56, 54

48, 32, 30

83

82

49

50

51

52

28

27

26

25

24

20

21

22

23

88

46

Mnemonic

FILT

VD

VDD

PVDD

DVDD

GND

SDA

SCL

DDCSCL

DDCSDA

PU2

PU1

S/PDIF

I2S0

I2S1

I2S2

I2S3

MCLKIN

MCLKOUT

SCLK

LRCLK

DE

RTERM

Function

Connection for External Filter Components for Audio PLL

Analog Power Supply and DVI Terminators

Value

PVDD

3.3 V

Output Power Supply

PLL Power Supply

Digital Logic Power Supply

Ground

Serial Port Data I/O

Serial Port Data Clock

HDCP Slave Serial Port Data Clock

HDCP Slave Serial Port Data I/O

This should be pulled up to 3.3 V through a 10 kΩ resistor

This should be pulled up to 3.3 V through a 10 kΩ resistor

S/PDIF Digital Audio Output

I2S Audio (Channel 1, Channel 2)

I2S Audio (Channels 3, Channel 4)

I2S Audio (Channels 5, Channel 6)

I2S Audio (Channels 7, Channel 8)

External Reference Audio Clock In

Audio Master Clock Output

Audio Serial Clock Output

Data Output Clock for Left and Right Audio Channels

Data Enable

Sets Internal Termination Resistance

1.8 V to 3.3 V

1.8 V

1.8 V

0V

3.3 V CMOS

3.3 V CMOS

3.3 V CMOS

3.3 V CMOS

3.3 V CMOS

3.3 V CMOS

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

3.3 V CMOS

500 Ω

Table 6. Pin Function Descriptions

Mnemonic

Description

INPUTS

Rx0+

Digital Input Channel 0 True.

Rx0−

Digital Input Channel 0 Complement.

Rx1+

Digital Input Channel 1 True.

Rx1−

Digital Input Channel 1 Complement.

Rx2+

Digital Input Channel 2 True.

Rx2−

Digital Input Channel 2 Complement.

These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel

rate) from a digital graphics transmitter.

RxC+

Digital Data Clock True.

RxC−

Digital Data Clock Complement.

This clock pair receives a TMDS clock at 1× pixel data rate.

FILT

External Filter Connection.

For proper operation, the audio clock generator PLL requires an external filter. Connect the filter shown in

Figure 8 to this pin. For optimal performance, minimize noise and parasitics on this node. For more information

see the PCB Layout Recommendations section .

PWRDN

Power-Down Control/Three-State Control.

The function of this pin is programmable via Register 0x26 [2:1].

Rev. 0 | Page 7 of 44

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