AD9434-370EBZ データシートの表示（PDF） - Analog Devices
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AD9434-370EBZ Datasheet PDF : 28 Pages
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Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D3– 1
D3+ 2
D4– 3
D4+ 4
D5– 5
D5+ 6
DRVDD 7
DRGND 8
D6– 9
D6+ 10
D7– 11
D7+ 12
D8– 13
D8+ 14
PIN 1
INDICATOR
AD9434
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 VREF
30 AVDD
29 PWDN
AD9434
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. AGND AND DRGND SHOULD BE TIED TO A COMMON
QUIET GROUND PLANE.
3. THE EXPOSED PADDLE MUST BE SOLDERED TO
A GROUND PLANE.
Figure 4. Pin Configuration—Single Data Rate Mode
Table 7. Pin Function Descriptions—Single Data Rate Mode
Pin No.
Mnemonic
Description
0
AGND 1
Analog Ground. The exposed paddle must be soldered to a ground plane.
30, 32 to 34, 37 to 39, AVDD
41 to 43, 46
1.8 V Analog Supply.
7, 24, 47
DRVDD
1.8 V Digital Output Supply.
8, 23, 48
DRGND1
Digital Output Ground.
35
VIN+
Analog Input—True.
36
VIN−
Analog Input—Complement.
40
CML
Common-Mode Output. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44
CLK+
Clock Input—True.
45
CLK−
Clock Input—Complement.
31
VREF
Voltage Reference Internal/Input/Output. Nominally 0.75 V.
28
DNC
Do Not Connect. Do not connect to this pin. This pin should be left floating.
25
SDIO
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).
26
SCLK/DFS
Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).
27
CSB
Serial Port Chip Select (Active Low).
29
PWDN
Chip Power-Down.
49
DCO−
Data Clock Output—Complement.
50
DCO+
Data Clock Output—True.
51
D0−
D0 Complement Output (LSB).
52
D0+
D0 True Output (LSB).
53
D1−
D1 Complement Output.
54
D1+
D1 True Output.
55
D2−
D2 Complement Output.
56
D2+
D2 True Output.
1
D3−
D3 Complement Output.
2
D3+
D3 True Output.
3
D4−
D4 Complement Output.
Rev. B | Page 9 of 28
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