AD9444 データシートの表示（PDF） - Analog Devices

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AD9444

14-Bit, 80 MSPS, A/D Converter

Analog Devices 

Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode

Pin No.

Mnemonic Description

Pin No.

1, 8 to 9, 16 to 18,

24 to 27, 34 to 35,

38, 41 to 42, 87,

89 to 95, 98

2 to 4, 7,

43 to 46, 49 to 52,

55 to 60, 65

5

AVDD1

DNC

OUTPUT

MODE

6

DFS

10

SENSE

11

VREF

12, 15, 20, 23,

32, 86, 88, 96 to

97, 99, Exposed

Heat Sink

AGND

3.3 V (±5%) Analog Supply.

Do Not Connect. These

pins should float.

CMOS Compatible Output

Logic Mode Control Pin.

OUTPUT MODE = 0 for CMOS

mode, and OUTPUT MODE =

1 (AVDD1) for LVDS outputs.

Data Format Select Pin.

CMOS control pin that de-

termines the format of the

output data. DFS = high

(AVDD1) for twos comple-

ment, DFS = low (ground) for

offset binary format.

Reference Mode Selection.

Connect to AGND for internal

1 V reference, and connect to

AVDD2 for external reference.

1.0 V Reference I/O—

Function Dependent on

SENSE. Decouple to ground

with 0.1 µF and 10 µF

capacitors.

Analog Ground. The exposed

heat sink on the bottom of

the package must be

connected to AGND.

33

36

37

47, 54, 62,

75, 83

48, 53, 61,

67, 74, 82

63

64

66

68

69

70

71

72

73

76

77

78

79

80

81

84

85

13

REFT

Differential Reference Out-

100

put. Decoupled to ground

with 0.1 µF capacitor and to

REFB (Pin 14) with 0.1 µF and

10 µF capacitors.

14

REFB

Differential Reference Out-

put. Decoupled to ground

with a 0.1 µF capacitor and to

REFT (Pin 13) with 0.1 µF and

10 µF capacitors.

19, 28 to 31,

39 to 40

AVDD2

5.0 V Analog Supply (±5%).

21

VIN+

Analog Input—True.

22

VIN−

Analog Input—Complement.

AD9444

Mnemonic

C1

CLK+

CLK−

DRVDD

DRGND

Description

Internal Bypass Node.

Connect a 0.1 µF capacitor

from this pin to AGND.

Clock Input—True.

Clock Input—Complement.

3.3 V Digital Output

Supply (2.5V to 3.6 V).

Digital Ground.

DCO−

DCO+

D0 (LSB)

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13 (MSB)

OR

DCS MODE

Data Clock Output—

Complement (CMOS Levels).

Data Clock Output—

True.

D0 Output Bit (LSB)

(CMOS Levels).

D1 Output Bit.

D2 Output Bit.

D3 Output Bit.

D4 Output Bit.

D5 Output Bit.

D6 Output Bit.

D7 Output Bit.

D8 Output Bit.

D9 Output Bit.

D10 Output Bit.

D11 Output Bit.

D12 Output Bit.

D13 Output Bit.

Out-of-Range Output.

Clock Duty Cycle Stabilizer

(DCS) Control Pin, CMOS-

Compatible. DCS = low

(AGND) to enable DCS

(recommended). DCS =

high (AVDD1) to disable DCS.

Rev. 0 | Page 13 of 40

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