AD9444 データシートの表示（PDF） - Analog Devices

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AD9444

14-Bit, 80 MSPS, A/D Converter

Analog Devices 

75

0.2ps

70

65

0.5ps

60

1.0ps

55

1.5ps

2.0ps

50

2.5ps

3.0ps

45

40

1

10

100

1000

INPUT FREQUENCY (MHz)

Figure 46. SNR vs. Input Frequency and Jitter

POWER CONSIDERATIONS

Care should be taken when selecting a power source. The use of

linear dc supplies is highly recommended. Switching supplies

tend to have radiated components that may be received by the

AD9444. Each of the power supply pins should be decoupled as

closely to the package as possible using 0.1 µF chip capacitors.

The AD9444 has separate digital and analog power supply

pins. The analog supplies are denoted AVDD1 (3.3 V) and

AVDD2 (5 V) and the digital supply pins are denoted DRVDD.

Although the AVDD1 and DRVDD supplies may be tied

together, best performance is achieved when the supplies are

separate. This is because the fast digital output swings can

couple switching current back into the analog supplies. Note

that both AVDD1 and AVDD2 must be held within 5% of the

specified voltage.

The DRVDD supply of the AD9444 is a dedicated supply for the

digital outputs, in either LVDS or CMOS output modes. When

in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS

mode, the DRVDD supply may be connected from 2.5 V to

3.6 V to be compatible with the receiving logic.

DIGITAL OUTPUTS

LVDS Mode

The off-chip drivers on the chip can be configured to provide

LVDS-compatible output levels via Pin 5 (OUTPUT MODE).

LVDS outputs are available when OUTPUT MODE is CMOS

logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET

resistor is placed at Pin 7 (LVDSBIAS) to ground. Dynamic

performance, including both SFDR and SNR, is maximized

when the AD9444 is used in LVDS mode, and designers are

encouraged to take advantage of this mode. The AD9444 out-

puts include complimentary LVDS outputs for each data bit

(DX+/DX−), the overrange output (OR+/OR−), and the output

data clock output (DCO+/DCO−). The RSET resistor current is

ratioed on-chip, setting the output current at each output equal

to a nominal 3.5 mA (11 × IRSET ). A 100 Ω differential termina-

AD9444

tion resistor placed at the LVDS receiver inputs results in a

nominal 350 mV swing at the receiver. LVDS mode facilitates

interfacing with LVDS receivers in custom ASICs and FPGAs

that have LVDS capability for superior switching performance

in noisy environments. Single point-to-point net topologies are

recommended with a 100 Ω termination resistor as close to the

receiver as possible. It is recommended to keep the trace length

less than 1 inch to 2 inches and to keep differential output trace

lengths as equal as possible.

CMOS Mode

In applications that can tolerate a slight degradation in dynamic

performance, the AD9444 output drivers can be configured to

interface with 2.5 V or 3.3 V logic families by matching DRVDD

to the digital supply of the interfaced logic. CMOS outputs are

available when OUTPUT MODE is CMOS logic low (or AGND

for convenience). In this mode, the output data bits are single-

ended CMOS, DX, as is the overrange output, OR. The output

clock is provided as a differential CMOS signal, DCO+/DCO−.

Lower supply voltages are recommended to avoid coupling

switching transients back to the sensitive analog sections of the

ADC. The capacitive load to the CMOS outputs should be

minimized, and each output should be connected to a single

gate through a series resistor (220 Ω) to minimize switching

transients caused by the capacitive loading.

TIMING

The AD9444 provides latched data outputs with a pipeline delay

of 12 clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and

Figure 3 for detailed timing diagrams.

OPERATIONAL MODE SELECTION

Data Format Select

The data format select (DFS) pin of the AD9444 determines

the coding format of the output data. This pin is 3.3 V CMOS

compatible, with logic high (or AVDD1, 3.3 V) selecting twos

complement, and DFS logic low (AGND) selecting offset binary

format. Table 10 summarizes the output coding.

Output Mode Select

The OUPUT MODE pin controls the logic compatibility,

as well as the pinout of the digital outputs. This pin is a CMOS

compatible input. With OUTPUT MODE = 0 (AGND), the

AD9444 outputs are CMOS-compatible and the pin assignment

for the device is defined in Table 8. With OUTPUT MODE = 1

(AVDD1, 3.3 V), the AD9444 outputs are LVDS-compatible and

the pin assignment for the device is defined in Table 7.

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS MODE pin; a CMOS

logic low (AGND) on DCS MODE enables the DCS, and logic

high (AVDD1, 3.3 V) disables the controller.

Rev. 0 | Page 23 of 40

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