AD9512-EP データシートの表示（PDF） - Analog Devices
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AD9512-EP Datasheet PDF : 20 Pages
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AD9512-EP
TIMING CHARACTERISTICS
Table 3.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT1
Divide = Bypass
Divide = 2 to 32
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS
OUT1 to OUT0 on Same Part, tSKP2
OUT1 to OUT2 on Same Part, tSKP2
OUT0 to OUT2 on Same Part, tSKP2
All LVPECL OUT Across Multiple Parts, tSKP_AB3
Same LVPECL OUT Across Multiple Parts, tSKP_AB3
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT1
OUT3 to OUT4
Divide = Bypass
Divide = 2 to 32
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS
OUT3 to OUT4 on Same Part, tSKV2
All LVDS OUTs Across Multiple Parts, tSKV_AB3
Same LVDS OUT Across Multiple Parts, tSKV_AB3
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT1
Divide = Bypass
Divide = 2 to 32
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS
OUT3 to OUT4 on Same Part, tSKC2
All CMOS OUT Across Multiple Parts, tSKC_AB3
Same CMOS OUT Across Multiple Parts, tSKC_AB3
LVPECL-TO-LVDS OUT
Output Skew, tSKP_V
LVPECL-TO-CMOS OUT
Output Skew, tSKP_C
Enhanced Product
Min Typ
130
130
320 490
335 490
360 545
375 545
0.5
70
100
15
45
45
65
200
210
Max Unit Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Output level 0x3D (0x3E) (0x3F)[3:2] = 10b
180 ps
20% to 80%, measured differentially
180 ps
80% to 20%, measured differentially
635 ps
At full temperature range
635 ps
At −40°C to +85°C
695 ps
At full temperature range
695 ps
At −40°C to +85°C
ps/°C
140 ps
80
ps
90
Ps
275 ps
130 ps
350 ps
350 ps
Termination = 100 Ω differential
Output level 0x40 (0x41) [2:1] = 01b
3.5 mA termination current
20% to 80%, measured differentially
80% to 20%, measured differentially
0.97 1.33
0.99 1.33
1.02 1.38
1.04 1.38
0.9
1.59 ns
At full temperature range
1.59 ns
At −40°C to +85°C
1.64 ns
At full temperature range
1.64 ns
At −40°C to +85°C
ps/°C
−85
681
646
+270 ps
450 ps
325 ps
865 ps
992 ps
B outputs are inverted; termination = open
20% to 80%; CLOAD = 3 pF
80% to 20%; CLOAD = 3 pF
1.0 1.39
1.02 1.39
1.05 1.44
1.07 1.44
1
1.71 ns
At full temperature range
1.71 ns
At −40°C to +85°C
1.76 ns
At full temperature range
1.76 ns
At −40°C to +85°C
ps/°C
−140 +145 +300 ps
650 ps
500 ps
0.73 0.92 1.14 ns
0.87 1.14 1.43 ns
Everything the same; different logic type
LVPECL to LVDS on same part
Everything the same; different logic type
LVPECL to CMOS on same part
Rev. 0 | Page 4 of 20
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