AD9513(Rev0) データシートの表示（PDF） - Analog Devices
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AD9513 Datasheet PDF : 28 Pages
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AD9513
Parameter
DELAY BLOCK ADDITIVE TIME JITTER1
Delay FS = 1.8 ns Fine Adj. 00000
Delay FS = 1.8 ns Fine Adj. 11111
Delay FS = 6.0 ns Fine Adj. 00000
Delay FS = 6.0 ns Fine Adj. 11111
Delay FS = 11.6 ns Fine Adj. 00000
Delay FS = 11.6 ns Fine Adj. 11111
Min Typ Max Unit
0.71
ps rms
1.2
ps rms
1.3
ps rms
2.7
ps rms
2.0
ps rms
2.8
ps rms
Test Conditions/Comments
100 MHz output; incremental additive jitter1
1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter
Min
Typ
SYNCB
Logic High
2.7
Logic Low
Capacitance
2
VREF
Output Voltage
0.62·VS
S0 TO S10
Levels
0
1/3
0.2·VS
2/3
0.55·VS
1
0.9·VS
Max
0.40
0.76·VS
0.1·VS
0.45·VS
0.8·VS
Unit Test Conditions/Comments
V
V
pF
V
Minimum − maximum from 0 mA to 1 mA load
V
V
V
V
POWER
Table 7.
Parameter
POWER-ON SYNCHRONIZATION1
VS Transit Time from 2.2 V to 3.1 V
POWER DISSIPATION
POWER DELTA
Divider (Divide = 2 to Divide = 1)
LVDS Output
CMOS Output (Static)
CMOS Output (@ 62.5 MHz)
CMOS Output (@ 125 MHz)
Delay Block
Min Typ Max Unit Test Conditions/Comments
35 ms See the Power-On SYNC section.
175 325 575 mW All three outputs on. LVDS (divide = 2). No clock. Does not include
power dissipated in external resistors.
240 460 615 mW All three outputs on. CMOS (divide = 2); 62.5 MHz out (5 pF load).
320 605 840 mW All three outputs on. CMOS (divide = 2); 125 MHz out (5 pF load).
15 30 45 mW For each divider. No clock.
20 50 85 mW No clock.
30 40 50 mW No clock.
65 110 155 mW Single-ended. At 62.5 MHz out with 5 pF load.
70 145 220 mW Single-ended. At 125 MHz out with 5 pF load.
30 45 65 mW Off to 1.8 ns fs, delay word = 60; output clocking at 62.5 MHz.
1 This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs are not synchronized.
Rev. 0 | Page 9 of 28
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