AD9525(Rev0) データシートの表示（PDF） - Analog Devices

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AD9525
(Rev.:Rev0)

Low Jitter Clock Generator with Eight LVPECL Outputs

Analog Devices 

Data Sheet

AD9525

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 2.05 GHZ VCO)

Table 14.

Parameter

LVPECL OUTPUT ABSOLUTE TIME JITTER

FOUT = 2048.867 MHz

Reference Sideband Spurs

Min Typ

Max Unit

Test Conditions/Comments

Application example based on a typical setup using

an external 2.05 MHz VCO (Bowei Model MVCO-

2050A); reference = 122.054215 MHz; R divider = 12;

PLL LBW = 5 kHz

19

fs rms Integration BW = 200 kHz to 5 MHz

21

fs rms Integration BW = 200 kHz to 10 MHz

87

fs rms Integration BW = 12 kHz to 20 MHz

−105

dBc

±10.671MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 3 GHZ VCO)

Table 15.

Parameter

LVPECL OUTPUT ABSOLUTE TIME JITTER

FOUT = 2949.12 MHz; PLL LBW = 7 kHz

Reference Sideband Spurs

FOUT = 1474.56 MHz; PLL LBW = 7 kHz

Reference Sideband Spurs

FOUT = 491.52 MHz; PLL LBW = 7 kHz

Reference Sideband Spurs

Min Typ Max Unit

63

38

34

28

−99

62

36

31

25

−100

78

60

44

33

−96

fs rms

fs rms

fs rms

fs rms

dBc

fs rms

fs rms

fs rms

fs rms

dBc

fs rms

fs rms

fs rms

fs rms

dBc

Test Conditions/Comments

Application example based on a typical setup using

an external 2950 MHz VCO (Z-Communications Model

CRO-2950); reference = 122.88 MHz; R divider = 1

Integration BW = 1 kHz to 100 MHz

Integration BW = 10 kHz to 100 MHz

Integration BW = 10 kHz to 40 MHz

Integration BW = 12 kHz to 20 MHz

±122.88 MHz

Integration BW = 1 kHz to 100 MHz

Integration BW = 10 kHz to 100 MHz

Integration BW = 10 kHz to 40 MHz

Integration BW = 12 kHz to 20 MHz

±122.88 MHz

Integration BW = 1 kHz to 100 MHz

Integration BW = 10 kHz to 100 MHz

Integration BW = 10 kHz to 40 MHz

Integration BW = 12 kHz to 20 MHz

±122.88 MHz

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; CLOCK INPUT TO DISTRIBUTION OUTPUT,

INCLUDING VCO DIVIDER)

Table 16.

Parameter

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 2949.12 MHz, FOUT = 2949.12 MHz

Divider = 1

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 800 kHz Offset

At 1 MHz Offset

At 10 MHz Offset

At 100 MHz Offset

Min Typ

Max Unit

Test Conditions/Comments

Distribution section only; does not include PLL and VCO

−112

−122

−133

−141

−146

−148

−148

−149

−151

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

Rev. 0 | Page 9 of 48

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