AD9547/PCBZ データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD9547/PCBZ Datasheet PDF : 106 Pages
| |||
AD9547
Data Sheet
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter
Min
EEPROM-TO-REGISTER DOWNLOAD TIME
REGISTER-TO-EEPROM UPLOAD TIME
MINIMUM POWER-DOWN EXIT TIME
MAXIMUM TIME FROM ASSERTION OF THE RESET PIN
TO THE M0 TO M7 PINS ENTERING HIGH
IMPEDANCE STATE
Typ Max Unit
25
ms
200
ms
10.5
µs
45
ns
Test Conditions/Comments
Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F)
Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F)
Dependent on loop filter bandwidth
DIGITAL PLL
Table 14.
Parameter
PHASE FREQUENCY DETECTOR (PFD) INPUT
FREQUENCY RANGE
LOOP BANDWIDTH
PHASE MARGIN
REFERENCE INPUT (R) DIVISION FACTOR
INTEGER FEEDBACK (S) DIVISION FACTOR
FRACTIONAL FEEDBACK DIVIDE RATIO
Min
Typ
0.001
0.001
30
1
8
0
Max Unit
10
MHz
Test Conditions/Comments
Maximum fPFD = fS/1001, 2
1 × 105
89
230
220
0.999
Hz
Degrees
Programmable design parameter;
maximum fLOOP = fREF/(20R)3
Programmable design parameter
1, 2, …1,073,741,824
8, 9, …1,048,576
Maximum value = 1022/1023
1 fPFD is the frequency at the input to the phase-frequency detector.
2 fS is the sample rate of the output DAC.
3 fREF is the frequency of the active reference; R is the frequency division factor determined by the R divider.
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter
PHASE LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
FREQUENCY LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
Min
Typ
0.001
1
0.001
1
Max Unit
65.5 ns
ps
16,700 ns
ps
Test Conditions/Comments
Reference-to-feedback period difference
HOLDOVER SPECIFICATIONS
Table 16.
Parameter
FREQUENCY ACCURACY
Min
Typ
Max Unit
<0.01
ppb
Test Conditions/Comments
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference
prior to entering holdover
Rev. G | Page 10 of 106
Share Link: 