AD9547/PCBZ データシートの表示（PDF） - Analog Devices
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AD9547/PCBZ Datasheet PDF : 106 Pages
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Data Sheet
AD9547
LOGIC INPUTS (M0 TO M7, RESET)
Table 4.
Parameter
INPUT VOLTAGE
Input High Voltage (VIH)
Input Low Voltage (VIL)
INPUT CURRENT (IINH, IINL)
INPUT CAPACITANCE (CIN)
Min Typ Max Unit Test Conditions/Comments
2.1
V
0.8
V
±80 ±200 µA
3
pF
LOGIC OUTPUTS (M0 TO M7, IRQ)
Table 5.
Parameter
OUTPUT VOLTAGE
Output High Voltage (VOH)
Output Low Voltage (VOL)
IRQ LEAKAGE CURRENT
Active Low Output Mode
Active High Output Mode
Min Typ Max Unit Test Conditions/Comments
2.7
V
IOH = 1 mA
0.4
V
IOL = 1 mA
Open-drain mode
1
µA
VOH = 3.3 V
1
µA
VOL = 0 V
SYSTEM CLOCK INPUTS (SYSCLKP, SYSCLKN)
Table 6.
Parameter
SYSTEM CLOCK PLL BYPASSED
Input Frequency Range
Minimum Input Slew Rate
Duty Cycle
Common-Mode Voltage
Differential Input Voltage Sensitivity
Min Typ
500
1000
40
1.2
100
Input Capacitance
Input Resistance
SYSTEM CLOCK PLL ENABLED
PLL Output Frequency Range
Phase Frequency Detector (PFD) Rate
Frequency Multiplication Range
VCO Gain
High Frequency Path
Input Frequency Range
Minimum Input Slew Rate
Frequency Divider Range
Common-Mode Voltage
Differential Input Voltage Sensitivity
2
2.5
900
6
70
100.1
200
1
1
100
Input Capacitance
3
Input Resistance
2.5
Max
1000
60
1000
150
255
500
8
Unit
Test Conditions/Comments
MHz
V/µs
%
V
mV p-p
pF
kΩ
Minimum limit imposed for jitter performance
Internally generated
Minimum voltage across pins is required to ensure
switching between logic states; the instantaneous
voltage on either pin must not exceed the supply rails;
ac ground the unused input to accommodate
single-ended operation
Single-ended, each pin
MHz
MHz
MHz/V
Assumes valid system clock and PFD rates
MHz
V/µs
V
mV p-p
pF
kΩ
Minimum limit imposed for jitter performance
Binary steps (M = 1, 2, 4, 8)
Internally generated
This is the minimum voltage required across the pins to
ensure switching between logic states; the
instantaneous voltage on either pin must not exceed
the supply rails; ac ground the unused input to
accommodate single-ended operation
Single-ended, each pin
Rev. G | Page 5 of 106
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