AD9547/PCBZ データシートの表示（PDF） - Analog Devices

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AD9547/PCBZ

Dual/Quad Input Network Clock Generator/Synchronizer

Analog Devices 

Data Sheet

Parameter

Min

Typ

Max

Rise/Fall Time1 (20% to 80%)

3.3 V Supply

Strong Drive Strength Setting

0.5

2

Weak Drive Strength Setting

8

14.5

1.8 V Supply

1.5

2.5

Duty Cycle

40

60

Output Voltage High (VOH)

AVDD3 = 3.3 V, IOH = 10 mA

2.6

AVDD3 = 3.3 V, IOH = 1 mA

2.9

AVDD3 = 1.8 V, IOH = 1 mA

1.5

Output Voltage Low (VOL)

AVDD3 = 3.3 V, IOL = 10 mA

AVDD3 = 3.3 V, IOL = 1 mA

AVDD3 = 1.8 V, IOL = 1 mA

OUTPUT TIMING SKEW

Between LVPECL Outputs

Between LVDS Outputs

Between CMOS (3.3 V) Outputs

Strong Drive Strength Setting

Weak Drive Strength Setting

Between CMOS (1.8 V) Outputs

Between LVPECL Outputs and LVDS

Outputs

Between LVPECL Outputs and

CMOS Outputs

ZERO-DELAY TIMING SKEW

0.3

0.1

0.1

14

125

13

138

23

240

24

40

14

140

19

±5

1 The listed values are for the slower edge (rising or falling).

DAC OUTPUT CHARACTERISTICS (DACOUTP, DACOUTN)

Table 12.

Parameter

FREQUENCY RANGE

OUTPUT OFFSET VOLTAGE

Min

Typ

Max

62.5

450

15

VOLTAGE COMPLIANCE RANGE

OUTPUT RESISTANCE

OUTPUT CAPACITANCE

FULL-SCALE OUTPUT CURRENT

GAIN ERROR

VSS − 0.5

0.5

50

5

20

−12

VSS + 0.5

+12

AD9547

Unit Test Conditions/Comments

10 pF load

ns

ns

ns

%

10 pF load

Output driver static; strong drive

strength setting

V

V

V

Output driver static; strong drive

strength setting

V

V

V

10 pF load

ps

Rising edge only; any divide value

ps

Rising edge only; any divide value

ps

ps

ps

Weak drive option not supported at 1.8 V

ps

ps

ns

Output relative to active input reference;

output distribution synchronization to

active reference feature enabled;

assumes manual phase offset

compensation of deterministic latency

Unit

MHz

mV

V

Ω

pF

mA

% FS

Test Conditions/Comments

This is the single-ended voltage at either

DAC output pin (no external load) when

the internal DAC code is such that no

current is delivered to that pin

Single-ended; each pin has an internal

50 Ω termination to VSS

Programmable (8 mA to 31 mA; see the

DAC Output section)

Rev. G | Page 9 of 106

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