AD9548 データシートの表示（PDF） - Analog Devices
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AD9548 Datasheet PDF : 111 Pages
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AD9548
Data Sheet
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter
Min
TIME DURATION OF DIGITAL FUNCTIONS
EEPROM-to-Register Download Time
Register-to-EEPROM Upload Time
Minimum Power-Down Exit Time
Maximum Time from Assertion of the RESET
pin to the M0 to M7 Pins Entering High
Impedance State
DIGITAL PLL
Table 14.
Parameter
DIGITAL PLL
Phase-Frequency Detector (PFD)
Input Frequency Range
Loop Bandwidth
Min
Typ
1
0.001
Phase Margin
30
Reference Input (R) Division Factor 1
Integer Feedback (S) Division Factor 8
Fractional Feedback Divide Ratio
0
Typ
Max
Unit
Test Conditions/Comments
25
ms
Using default EEPROM storage
sequence (see Register 0x0E10 to
Register 0x0E3F)
200
ms
Using default EEPROM storage
sequence (see Register 0x0E10 to
Register 0x0E3F
10.5
μs
Dependent on loop-filter bandwidth
45
ns
Max
107
105
89
230
230
0.999
Unit
Test Conditions/Comments
Hz
Hz
Degrees
Maximum fPFD1: fS/1002
Programmable design parameter; maximum
fLOOP = fREF/(20R)3
Programmable design parameter
1, 2, …, 1,073,741,824
8, 9, …, 1,073,741,824
Maximum value: 1022/1023
1 fPFD is the frequency at the input to the phase-frequency detector.
2 fS is the sample rate of the output DAC.
3 fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider.
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter
Min
Typ
PHASE LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
0.001
1
FREQUENCY LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
0.001
1
Max
Unit
65.5
ns
ps
16,700 ns
ps
Test Conditions/Comments
Reference-to-feedback period difference
HOLDOVER SPECIFICATIONS
Table 16.
Parameter
HOLDOVER SPECIFICATIONS
Frequency Accuracy
Min
Typ
Max
Unit
<0.01
ppb
Test Conditions/Comments
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference prior
to entering holdover
Rev. G | Page 10 of 111
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