AD9548 データシートの表示（PDF） - Analog Devices

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AD9548

Quad/Octal Input Network Clock Generator/Synchronizer

Analog Devices 

Data Sheet

AD9548

Parameter

Min

Typ

Rise/Fall Time1 (20% to 80%)

3.3 V Supply

Strong Drive Strength Setting

0.5

Weak Drive Strength Setting

8

1.8 V Supply

1.5

Duty Cycle

40

Output Voltage High (VOH)

AVDD3 = 3.3 V, IOH = 10 mA

2.6

AVDD3 = 3.3 V, IOH = 1 mA

2.9

AVDD3 = 1.8 V, IOH = 1 mA

1.5

Output Voltage Low (VOL)

AVDD3 = 3.3 V, IOL = 10 mA

AVDD3 = 3.3 V, IOL = 1 mA

AVDD3 = 1.8 V, IOL = 1 mA

OUTPUT TIMING SKEW

Between LVPECL Outputs

14

Between LVDS Outputs

13

Between CMOS 3.3 V Outputs

Strong Drive Strength Setting

23

Weak Drive Strength Setting

24

Between CMOS 1.8 V Outputs

40

Between LVPECL Outputs and LVDS

14

Outputs

Between LVPECL Outputs and CMOS

19

Outputs

ZERO-DELAY TIMING SKEW

±5

Max

Unit

Test Conditions/Comments

10 pF load

2

ns

14.5

ns

2.5

ns

60

%

10 pF load

Output driver static; strong drive strength

setting

V

V

V

Output driver static; strong drive strength

setting

0.3

V

0.1

V

0.1

V

10 pF load

125

ps

Rising edge only; any divide value

138

ps

Rising edge only; any divide value

240

ps

ps

ps

Weak drive not supported at 1.8 V

140

ps

ps

ns

Output relative to active input reference;

output distribution synchronization to

active reference feature enabled; assumes

manual phase offset compensation of

deterministic latency

1 The listed values are for the slower edge (rise or fall).

DAC OUTPUT CHARACTERISTICS (DACOUTP/DACOUTN)

Table 12.

Parameter

DAC OUTPUT CHARACTERISTICS

(DACOUTP/DACOUTN)

Frequency Range

Output Offset Voltage

Voltage Compliance Range

Output Resistance

Output Capacitance

Full-Scale Output Current

Gain Error

Min

Typ

62.5

VSS − 0.5 0.5

50

5

20

−12

Max

Unit

Test Conditions/Comments

450

MHz

15

mV

VSS + 0.5 V

Ω

pF

mA

+12

% FS

This is the single-ended voltage at

either DAC output pin (no external

load) when the internal DAC code

implies that no current is delivered

to that pin.

Single-ended, each pin has an

internal 50 Ω termination to VSS.

Programmable (8 mA to 31 mA; see

the DAC Output section).

Rev. G | Page 9 of 111

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