AD9551BCPZ-REEL7 データシートの表示（PDF） - Analog Devices

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AD9551BCPZ-REEL7

1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

Analog Devices 

Parameter

Duty Cycle

Rise/Fall Time1 (20% to 80%)

Min

Typ

Max

45

55

500

745

1 The listed values are for the slower edge (rise or fall).

JITTER CHARACTERISTICS (180 HZ LOOP BANDWIDTH)

Table 3.

Parameter

JITTER GENERATION

12 kHz to 20 MHz

50 kHz to 80 MHz

4 MHz to 80 MHz

JITTER TRANSFER BANDWIDTH

Min

Typ

Max

1.3

0.8

0.5

0.6

0.1

180

JITTER TRANSFER PEAKING

0.1

CRYSTAL OSCILLATOR CHARACTERISTICS

Table 4.

Parameter

Min

CRYSTAL FREQUENCY

Range

19

Tolerance

CRYSTAL MOTIONAL RESISTANCE

DCXO LOAD CAPACITANCE CONTROL

RANGE

Typ

Max

26

52

20

100

3 to 21

POWER CONSUMPTION

Table 5.

Parameter

TOTAL CURRENT

VDD CURRENT BY PIN

Pin 9

Pin 23

Pin 27

Pin 34

LVPECL OUTPUT DRIVER

Min

Typ

Max

169

195

24

27

78

84

36

42

36

42

38

AD9551

Unit Test Conditions/Comments

%

At maximum output frequency

ps

3.3 V CMOS; standard drive strength

setting; 10 pF load

Unit Test Conditions/Comments

ps rms

ps rms

ps rms

ps rms

ps rms

Hz

dB

fIN = 19.44 MHz, fOUT = 622.08 MHz

fIN = 622.08 MHz, fOUT = 622.08 MHz

fIN = 19.44 MHz, fOUT = 622.08 MHz

fIN = 622.08 MHz, fOUT = 622.08 MHz

fIN = 622.08 MHz, fOUT = 622.08 MHz

See the Typical Performance

Characteristics section

See the Typical Performance

Characteristics section

Unit Test Conditions/Comments

MHz

ppm

Ω

pF

Requires a crystal with a 10 pF load

specification

Unit Test Conditions/Comments

mA

At maximum output frequency with both

output channels active

mA

mA

mA

mA

mA

900 MHz with 100 Ω termination between

both pins of the output driver

Rev. B | Page 5 of 40

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