AD9551BCPZ-REEL7 データシートの表示（PDF） - Analog Devices

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AD9551BCPZ-REEL7

1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

Analog Devices 

Parameter

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

Output

Output Logic 1 Voltage

Output Logic 0 Voltage

Min

Typ

1

1

2

2.8

SERIAL CONTROL PORT TIMING

Table 10.

Parameter

SCLK

Clock Rate, 1/tCLK

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO, tDV

CS to SCLK Setup (tS) and Hold (tH)

CS Minimum Pulse Width High

Limit

50

3

3

4

0

13

0

6.4

AD9551

Max

Unit Test Conditions/Comments

μA

μA

pF

V

1 mA load current

0.3

V

1 mA load current

Unit

MHz max

ns min

ns min

ns min

ns min

ns max

ns min

ns min

Rev. B | Page 7 of 40

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