DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

AD9551BCPZ-REEL7 データシートの表示(PDF) - Analog Devices

部品番号
コンポーネント説明
メーカー
AD9551BCPZ-REEL7 Datasheet PDF : 40 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9551
B2 1
B3 2
REFA 3
REFA 4
REFB 5
REFB 6
RESET 7
LDO_IPDIG 8
VDD 9
LDO_XTAL 10
PIN 1
INDICATOR
AD9551
TOP VIEW
(Not to Scale)
30 GND
29 OUT2
28 OUT2
27 VDD
26 OUTPUT PLL LOCKED
25 INPUT PLL LOCKED
24 LDO_1.8
23 VDD
22 LDO_VCO
21 Y0
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin
No.
Mnemonic
Type 1
9, 23, VDD
P
27, 34
30, 31 GND
P
4
REFA
I
3
REFA
I
5
REFB
I
6
REFB
I
13
CS
I
14
SCLK
I
15
SDIO
I/O
7
RESET
I
11
XTL0
I
12
XTL1
I
33
OUT1
O
32
OUT1
O
29
OUT2
O
28
OUT2
O
17
LF
I/O
26
OUTPUT PLL LOCKED O
25
INPUT PLL LOCKED O
16
OUTSEL
I
8
LDO_IPDIG
P/O
10
LDO_XTAL
P/O
22
LDO_VCO
P/O
24
LDO_1.8
P/O
35
A0
I
36
A1
I
37
A2
I
38
A3
I
Description
Power Supply Connection (3.3 V Analog Supply).
Analog Ground.
Analog Input (Active High)—Reference Clock Input A.
Analog Input (Active High)—Complementary Reference Clock Input A.
Analog Input (Active High)—Reference Clock Input B.
Analog Input (Active High)—Complementary Reference Clock Input B.
Digital Input Chip Select (Active Low).
Serial Data Clock.
Digital Serial Data Input/Output.
Digital Input (Active High). Resets internal logic to default states. This pin has an internal 100 kΩ
pull-up resistor, so the default state of the device is reset.
Pin for Connecting an External Crystal (20 MHz to 30 MHz).
Pin for Connecting an External Crystal (20 MHz to 30 MHz).
Square Wave Clocking Output 1.
Complementary Square Wave Clocking Output 1.
Square Wave Clocking Output 2.
Complementary Square Wave Clocking Output 2.
Loop Filter Node for the Output PLL. Connect an external 12 nF capacitor (100 nF in 19.44 MHz
mode) from this pin to Pin 22 ( LDO_VCO).
Active High Locked Status Indicator for the Output PLL.
Active High Locked Status Indicator for the Input PLL.
Logic 0 selects LVDS, and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2
when the outputs are not under SPI port control. Can be overridden via the programming registers.
LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground.
LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground.
LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground.
LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground.
Control Pin. Selects preset values for the REFA dividers.
Control Pin. Selects preset values for the REFA dividers.
Control Pin. Selects preset values for the REFA dividers.
Control Pin. Selects preset values for the REFA dividers.
Rev. B | Page 9 of 40

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]