AD9674 データシートの表示（PDF） - Analog Devices
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AD9674 Datasheet PDF : 47 Pages
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AD9674
Data Sheet
Parameter2
Close In SNR
Two-Tone Intermodulation Distortion
(IMD3)
LO Harmonic Rejection
Quadrature Phase Error
I/Q Amplitude Imbalance
Channel to Channel Matching
POWER SUPPLY
AVDD1
AVDD2
DVDD
DRVDD
IAVDD1
IAVDD2
IDVDD
IDRVDD
Total Power Dissipation (Including
Output Drivers)
Power-Down Dissipation
Standby Power Dissipation
ADC
Resolution
SNR
ADC REFERENCE
Output Voltage Error
Load Regulation at 1.0 mA
Input Resistance
Test Conditions/Comments
−3 dBFS input, fRF = 2.5 MHz,
fLO = 40 MHz, 1 kHz offset,
16LO5 mode, one channel enabled
−3 dBFS input, fRF = 2.5 MHz,
fLO = 40 MHz, 1 kHz offset,
16LO5 mode, eight channels enabled
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz,
fLO = 80 MHz, ARF1 = −1 dBFS,
ARF2 = −21 dBFS, IMD3 relative to ARF2
I to Q, all phases, 1 σ
I to Q, all phases, 1 σ
Phase I to I, Q to Q, 1 σ
Amplitude I to I, Q to Q, 1 σ
Mode I/Mode II/Mode III/Mode IV1, 3
TGC mode, LO band mode
CW Doppler mode
TGC mode, no signal, low band mode
TGC mode, no signal, high band mode
CW Doppler mode, eight channels
enabled
RF decimator enabled in Mode III1 and
Mode IV,1 digital HPF enabled
RF decimator enabled in Mode III1 and
Mode IV,1 digital HPF disabled
ANSI-644 mode
Low power (IEEE 1596.3 similar) mode
TGC mode, no signal, RF decimator
enabled in Mode III and Mode IV,
digital HPF disabled
TGC mode, no signal, RF decimator
enabled in Mode III1 and Mode IV, 1
digital HPF enabled
CW Doppler mode, eight channels
enabled
fIN = 5 MHz
VREF = 1 V
VREF = 1 V
Min Typ
156
Max
Unit
dBc/√Hz
161
dBc/√Hz
−58
dBc
0.15
0.015
0.5
0.25
−20
dBc
Degrees
dB
Degrees
dB
1.7 1.8
1.9
V
2.85 3.0
3.6
V
1.3 1.4
1.9
V
1.7 1.8
1.9
V
144/188/224/2943
mA
4
mA
230
mA
239
mA
140
mA
47/75/57/913
mA
30/48/42/653
mA
125/170/128/1693
mA
109/155/114/1543
mA
1190/1385/
1365/16003
1325/1535/ mW
1515/17653
1215/1425/
1385/16403
1350/1575/ mW
1535/18003
500
mW
30
mW
630
mW
14
Bits
75
dB
±50
mV
2
mV
7.5
kΩ
1 The ADC speed modes depending on the encoding clock rate.
2 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation.
3 The slashes mean that the four different power and current values are listed for the four different modes (Mode I, Mode II, Mode III, Mode IV).
4 The overrange condition is specified as 6 dB more than the full-scale input range.
5 The internal LO frequency, fLO, is generated from the supplied multiplier local oscillator frequency, fMLO, by dividing it up by a configurable divider value (M) that can be
4, 8, or 16; the MLO signal is named 4LO, 8LO, or 16LO, accordingly.
Rev. A | Page 6 of 47
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