AD9712JN データシートの表示（PDF） - Analog Devices
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AD9712JN Datasheet PDF : 8 Pages
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- RNRLOGDEVICES fRX-ON-DEnRND HOTLINE
Page 2~
AD9712/AD97-1S3PECIFICATIONS
ABSOLUTE MAXIMUM RATINGS!
Positive Supply Voltage (+Vs)(AD9713 Only) . . . . . . . .+6 V
Negative Supply Voltage (-Vs)
(AD9712andAD9713)
7V
DAC Outputs to ANALOG RETURN . . . . . .+0.5V to -2 V
Digital Input Voltages (D1-D12' LATCH ENABLE)
AD9712
0Vto-Vs
AD9713
0Vto+Vs
Internal Reference Output Current. . . . . - 20 JLAto + 500 fLA
Control Amplifier Input Voltage Range . . . . . . . .0Vto -4 V
ControlAmplifierOutputCurrent
.:!:2.5mA
REFERENCE IN Voltage Range. . . . . . . . . .-3.7 V to -Vs
Analog Output Current (lOUT or lOUT)
.30 mA
Operating TemperatUre Range
AD9712]NIJP
Oto+70DC
AD9713]N/]P
Oto+70DC
Maximum Junction Temperature2 . . . . . . . . . . . . . . .+IS0.C
Lead TemperatUre (Soldering, 10 seconds) . . . . . . . . .+ 300DC
Storage TemperatUre Range
.-65°C to + IS0DC
= = = ELECTRICALCHARACTERISTICS(-Vs -5.2 V;+vs +5 V(AD9713 Only); CONTROLAMP IN -1.2 V
= Parameter (Conditions)
RESOLUTION
DC ACCURACY
Differential Nonlinearity Q)
OIntegral Nonlinearity Q)
B «<Best Fit" Straight Line)
S INITIAL OFFSET ERROR
Zero-SC4UeOffset Error
O Full-Scale Gain Error3
LE Offset Drift Coefficient
T REFERENCE/CONTROL AMP
E Internal Reference Voltage
(external); R$ET 1.5 kG, unlessotherwisenoted)
Test AD9112JN/JP
Temp Level MiD Typ Max
12
AD9713JNIJP
MiD Typ Max Units
12
Bits
+ 25"C I
Full VI
+ 25"C I
Full VI
1.2 2.0
4.0
3.0
4.0
1.2
2.0
LSB
4.0
LSB
3.0
LSB
4.0
LSB
+25°C I
Full VI
+2sDC I
Full VI
+25OC V
0.5
1.5
5.0
4.0
8.5
11.0
0.03
0.5
1.5
IJoA
5.0
IJoA
4.0
8.5
%
11.0 %
0.03
p.ArC
+25OC I
-1.13 - 1.26 - 1.39 -1.13 -1.26 - 1.39 V
Full I
-1.11
-1.41 -1.11
-1.41 V
Internal Reference Voltage Drift
Full
V
300
300
IJoV/oc
Amplifier Input Impedance
+25°C V
50
50
kO
Amplifier Bandwidth
+2SoC V
300
300
kHz
REFERENCE INPtYf4
Reference Input Impedance
+25°C V
3
Reference Multiplying Bandwidths +2SoC V
40
3
kf!
40
MHz
OtITPUT PERFORMANCE
Full-Scale Output Currenr6
Output Compliance Range
Output Resistance
Output Capacitance
Output Update Rate7
Output Settling Time (tST)S
Current Settling
Voltage Settling (RL = 50 fi)
Output Propagation Delay (tpD)9
Glitch Impulse1O
Output Slew Ratell
Output Rise Timeu
Output Fall Timell
+ 25°C V
+ 25OC IV
+25°C IV
+2sDC V
+25DC IV
+2SoC V
+2SoC V
+2SoC V
+2SoC V
+2SoC V
+2SOC V
+25OC V
20.48
-1.2
+3
2.0
2.5
3.0
30
100 110
30
30
8
100
400
3
2
20.48
-1.2
+3
2.0
2.5
3.0
30
80
90
30
30
11
100
400
3
2
mA
V
kf!
pF
M,SPS
ns
ns
ns
pV-s
V/s
ns
ns
-2-
REV.A
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