AD9755 データシートの表示（PDF） - Analog Devices
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AD9755 Datasheet PDF : 28 Pages
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AD9755
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
ADDITIONAL
EXTERNAL
LOAD
AD9755
REFERENCE
SECTION
AVDD
0.1F
1.2V REF
REFIO
FSADJ
CURRENT
SOURCE
ARRAY
IREF 2k⍀
Figure 4. Internal Reference Configuration
AVDD
EXTERNAL
REFERENCE
IREF
AD9755
REFERENCE
SECTION
AVDD
1.2V REF
REFIO
FSADJ
CURRENT
SOURCE
ARRAY
2k⍀
PORT 1
DATA IN
PORT 2
tS
tH
DATA X
DATA Y
CLK
IOUTA OR IOUTB
t LPW
t PD
DATA X
DATA Y
1/2 CYCLE + tPD
Figure 7a. DAC Input Timing Requirements
with PLL Active, Single Clock Cycle
PORT 1
DATA IN
PORT 2
DATA W
DATA X
DATA Y
DATA Z
Figure 5. External Reference Configuration
CLK
PLL CLOCK MULTIPLIER OPERATION
The Phase-Locked Loop (PLL) is intrinsic to the operation of the
AD9755 in that it produces the necessary internally synchronized
2× clock for the edge-triggered latches, multiplexer, and DAC.
With PLLVDD connected to its supply voltage, the AD9755 is in
PLL active mode. Figure 6 shows a functional block diagram of
the AD9755 clock control circuitry with PLL active. The
circuitry consists of a phase detector, charge pump, voltage
controlled oscillator (VCO), input data rate range control, clock
logic circuitry, and control input/outputs. The ÷ 2 logic in the
feedback loop allows the PLL to generate the 2× clock needed for
the DAC output latch.
Figure 7 defines the input and output timing for the AD9755
with the PLL active. CLK in Figure 7 represents the clock that
is generated external to the AD9755. The input data at both
Ports 1 and 2 is latched on the same CLK rising edge. CLK may
be applied as a single ended signal by tying CLK– to mid supply
and applying CLK to CLK+, or as a differential signal applied
to CLK+ and CLK–.
RESET has no purpose when using the internal PLL and should
be grounded. When the AD9755 is in PLL active mode,
PLLLOCK is the output of the internal phase detector. When
locked, the lock output in this mode is Logic 1.
CLKVDD
(3.0V TO 3.6V) PLLLOCK
392⍀ 1.0F
LPF PLLVDD
3.0V TO
3.6V
IOUTA OR IOUTB
XXX
DATA W DATA X
DATA Y DATA Z
Figure 7b. DAC Input Timing Requirements
with PLL Active, Multiple Clock Cycles
Typically, the VCO can generate outputs of 100 MHz to 400 MHz.
The range control is used to keep the VCO operating within its
designed range while allowing input clocks as low as 6.25 MHz.
With the PLL active, logic levels at DIV0 and DIV1 determine
the divide (prescaler) ratio of the range controller. Table I gives
the frequency range of the input clock for the different states of
DIV0 and DIV1.
Table I. CLK Rates for DIV0, DIV1 Levels with PLL Active
CLK Frequency
50 MHz–150 MHz
25 MHz–100 MHz
12.5 MHz–50 MHz
6.25 MHz–25 MHz
DIV1
0
0
1
1
DIV0
0
1
0
1
Range Controller
÷1
÷2
÷4
÷8
A 392 Ω resistor and 1.0 µF capacitor connected in series from
LPF to PLLVDD are required to optimize the phase noise versus
settling/acquisition time characteristics of the PLL. To obtain
optimum noise and distortion performance, PLLVDD should be
set to a voltage level similar to DVDD and CLKVDD.
CLK+
CLK–
DIFFERENTIAL-
TO-
SINGLE-ENDED
AMP
PHASE
DETECTOR
TO INPUT
LATCHES
AD9755
CHARGE
PUMP
VCO
RANGE
CONTROL
(،1, 2, 4, 8)
،2
TO DAC
LATCH
CLKCOM
DIV0
DIV1
Figure 6. Clock Circuitry with PLL Active
In general, the best phase noise performance for any PLL range
control setting is achieved with the VCO operating near its
maximum output frequency of 400 MHz.
As stated earlier, applications requiring input data rates below
6.25 MSPS must disable the PLL clock multiplier and provide
an external 2× reference clock. At higher data rates however,
applications already containing a low phase noise (i.e., jitter)
reference clock that is twice the input data rate should consider
disabling the PLL clock multiplier to achieve the best SNR
performance from the AD9755. Note that the SFDR performance
of the AD9755 remains unaffected with or without the PLL clock
multiplier enabled.
REV. B
–11–
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