AD9764 データシートの表示（PDF） - Analog Devices

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AD9764

14-Bit, 125 MSPS TxDAC® D/A Converter

Analog Devices 

PIN CONFIGURATION

(MSB) DB13 1

28 CLOCK

DB12 2

27 DVDD

DB11 3

26 DCOM

DB10 4

25 NC

DB9 5 AD9764 24 AVDD

DB8 6 TOP VIEW 23 COMP2

DB7 7 (Not to Scale) 22 IOUTA

DB6 8

21 IOUTB

DB5 9

20 ACOM

DB4 10

19 COMP1

DB3 11

18 FS ADJ

DB2 12

17 REFIO

DB1 13

16 REFLO

DB0 14

15 SLEEP

NC = NO CONNECT

AD9764

Pin No.

1

2–13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PIN FUNCTION DESCRIPTIONS

Name

Description

DB13

Most Significant Data Bit (MSB).

DB12–DB1 Data Bits 1–12.

DB0

Least Significant Data Bit (LSB).

SLEEP

Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if

not used.

REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to

AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).

Requires 0.1 µF capacitor to ACOM when internal reference activated.

FS ADJ Full-Scale Current Output Adjust.

COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.

ACOM Analog Common.

IOUTB

IOUTA

COMP2

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.

AVDD

Analog Supply Voltage (+2.7 V to +5.5 V).

NC

No Internal Connection.

DCOM Digital Common.

DVDD

Digital Supply Voltage (+2.7 V to +5.5 V).

CLOCK Clock Input. Data latched on positive edge of clock.

REV. C

–5–

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